nor_bootinit.s

Boot code for ADM5120 with serial console for Edimax router.

/*****************************************************************************
;
;   (C) Unpublished Work of ADMtek Incorporated.  All Rights Reserved.
;
;       THIS WORK IS AN UNPUBLISHED WORK AND CONTAINS CONFIDENTIAL,
;       PROPRIETARY AND TRADESECRET INFORMATION OF ADMTEK INCORPORATED.
;       ACCESS TO THIS WORK IS RESTRICTED TO (I) ADMTEK EMPLOYEES WHO HAVE A
;       NEED TO KNOW TO PERFORM TASKS WITHIN THE SCOPE OF THEIR ASSIGNMENTS
;       AND (II) ENTITIES OTHER THAN ADMTEK WHO HAVE ENTERED INTO APPROPRIATE
;       LICENSE AGREEMENTS.  NO PART OF THIS WORK MAY BE USED, PRACTICED,
;       PERFORMED, COPIED, DISTRIBUTED, REVISED, MODIFIED, TRANSLATED,
;       ABBRIDGED, CONDENSED, EXPANDED, COLLECTED, COMPILED, LINKED, RECAST,
;       TRANSFORMED OR ADAPTED WITHOUT THE PRIOR WRITTEN CONSENT OF ADMTEK.
;       ANY USE OR EXPLOITATION OF THIS WORK WITHOUT AUTHORIZATION COULD
;       SUBJECT THE PERPERTRATOR TO CRIMINAL AND CIVIL LIABILITY.
;
;------------------------------------------------------------------------------
;
;    Project : ADM5120
;    Creator : 
;    File    : bootinit.S
;    Abstract: 
;
;Modification History:
; 
;
;*****************************************************************************/


#include <mips.h>
#include <mips4kc.h>
#include <asm.h>
#include <adm5120.h>
#include <hw5120cfg.h>

	
.set noreorder
.set noat

.text
.org 0
VECTOR(romreset_except, unknown)
	/* Read current status */
	mfc0 	k0, CP0_STATUS_REG
	
	/* Is this a NMI */
	li		k1, CP0_STATUS_NMI_BIT
	and		k1, k0, k1
	beqz	k1, 2f						/* Branch if this is not a NMI. */
	nop									/* Branch delay slot */

	/* NMI wrapper */
	li 		k1, CP0_STATUS_BEV_BIT
	and		k1, k0, k1
1:	
	bnez	k1, 1b						/* Is the program ready to take a NMI */
	nop									/* Branch delay slot */
	
	/* Redirect the NMI to the handler in SDRAM */
	/*
	 *  !!!!  Not implemented yet   !!!!
	 */
1:
	b		1b
	nop
	
2:
	/*  Cold boot or Software reset  */

	/*=====  Initialize CP0 register  ====*/
	/* Set IV bit */	
	li 		t0, CP0_CAUSE_IV_BIT
	mtc0	t0, CP0_CAUSE_REG
	
	/* Clear watch register */	
	mtc0	zero, CP0_WATCHLO_REG
	mtc0	zero, CP0_WATCHHI_REG
	
	/* Set status register */
	li 		t0, CP0_STATUS_DEFAULT		/* defined as CP0_STATUS_BEV_BIT */
	mtc0	t0, CP0_STATUS_REG

	/* NOTE: CP0_CONFIG0_DEFAULT defined as CP0_CONFIG0_K0COHERENCY_DEFAULE */
	/* which is defined as CACHECTRL_UNCACHED if KSEG0_UNCACHED is defined  */
	/* and CACHECTRL_WRITE_THR_MODE if KSEG0_UNCACHED is not defined.       */
	/* NOTE2: KSEG0_UNCACHED is not defined anywhere so CP0_CONFIG0_DEFAULT */
	/* is set to CACHECTRL_WRITE_THR_MODE, or 3, which means "cacheable".   */

	/* Set configure 0 register */
	li 		t0, CP0_CONFIG0_DEFAULT
	mtc0	t0, CP0_CONFIG0_REG

//	jal		init_mpmc_sram
	bal		init_mpmc_sram
	nop

#ifndef KSEG0_UNCACHED
	// Init cache
//	jal		_C_LABEL(init_cache)
	bal		_C_LABEL(init_cache)
	nop									/* Branch delay slot */
#endif
	
	/*====  Jump to KSEG0 with cache enabled  ====*/
	la		t0, 1f
	jr		t0
	nop									/* Branch delay slot */
	
1:	
	/*  In KSEG0, cached  */
//	jal		init_mpmc_sdram
	bal		init_mpmc_sdram
	nop
	
	la		a0, _C_LABEL(romreset_except)
	addu	a0, a0, 0x1000
	jr		a0
	nop									/* Branch delay slot */
	
	/* Not reached here */
3:	
	b		3b
	nop									/* Branch delay slot */
VECTOR_END(romreset_except)

.org 0x200
VECTOR(romTLBrefill_except, unknown)
	/*
	 *	The exception is not handled here.
	 */
	
1:
	b		1b
	nop									/* Branch delay slot */
VECTOR_END(romTLBrefill_except)

.org 0x380
VECTOR(romgeneral_except, unknown)
	/*
	 *  Filter out the interrupt except and redirect it to interrupt_except
	 */

	mfc0	k0, CP0_CAUSE_REG
	and		k0, k0, CP0_CAUSE_EXCCODE_MASK
	srl		k0, k0, CP0_CAUSE_EXCCODE_SHIFT
	subu	k0, k0, EXCCODE_INT
	beqz	k0, _C_LABEL(romint_except)
	nop									/* Branch delay slot */
	
	/*
	 *  Not ready for handling exception yet.
	 */
1:
	b		1b
	nop									/* Branch delay slot */
	
VECTOR_END(romgeneral_except)

.org 0x400
VECTOR(romint_except, unknown)
	/*
	 *  We are not ready to handle interrupt here.
	 *  Clear the IE (interrupt enablet) bit and return
	 */
	mfc0	k0, CP0_STATUS_REG
	li		k1, ~CP0_STATUS_IE_BIT
	and		k0, k0, k1
	mtc0	k0, CP0_STATUS_REG
	eret
	
VECTOR_END(romint_except)

.org 0x480
VECTOR(romdbg_except, unknown)
	mfc0	k0, CP0_STATUS_REG
	
	/* Is the system ready to tak a debug exception */
	li 		k1, CP0_STATUS_BEV_BIT
	and 	k1, k0, k1
1:
	bnez	k1, 1b						/* Stop here if BEV is set */
	nop									/* Branch delay slot */

	/* Redirect the exception to the handler in SDRAM */
	/*
	 *  !!!!  Not implemented yet   !!!!
	 */
	
	/*	Not reached */	
2:
	b		2b
	nop									/* Branch delay slot */
VECTOR_END(romdbg_except)

.set at
.set reorder


.org 0x500
.set noreorder
LEAF(init_cache)
	/*====  Initialize Cache  ====*/

	/* Read cache configuration  */
#if 1
	mfc0	a0, CP0_CONFIG1_REG, CP0_CONFIG1_SEL

	/*  Determine ICACHE size  */
	li		t0, CP0_CONFIG1_IL_MASK
	and		t0, t0, a0
	srl		t0, t0, CP0_CONFIG1_IL_SHIFT
	
	beqz	t0, 1f
	li		s0, 0								/* Branch delay slot */
	// ICACHE line size is 16 bytes
	li		s1, 0x10

	li		t0, CP0_CONFIG1_IS_MASK
	and		t0, t0, a0
	srl		t0, t0, CP0_CONFIG1_IS_SHIFT
	li		t1, 64
	sll		t1, t1, t0							// lines per way
	
	li		t0, CP0_CONFIG1_IA_MASK	
	and		t2, t0, a0
	srl		t2, t2, CP0_CONFIG1_IA_SHIFT
	addiu	t2, t2, 1							// Number of way

	mul		t0, t1, t2							// total ICACHE line number
	mul		s0, t0, s1							// ICACHE size

1:
	/*  Determine DCACHE size  */
	li		t0, CP0_CONFIG1_DL_MASK
	and		t0, t0, a0
	srl		t0, t0, CP0_CONFIG1_DL_SHIFT
	
	beqz	t0, 2f
	li		s2, 0								/* Branch delay slot */
	// DCACHE line size is 16 bytes
	li		s3, 0x10

	li		t0, CP0_CONFIG1_DS_MASK
	and		t0, t0, a0
	srl		t0, t0, CP0_CONFIG1_DS_SHIFT
	li		t1, 64
	sll		t1, t1, t0							// lines per way

	li		t0, CP0_CONFIG1_DA_MASK	
	and		t2, t0, a0
	srl		t2, t2, CP0_CONFIG1_DA_SHIFT
	addiu	t2, t2, 1							// Number of way

	mul		t0, t1, t2							// total ICACHE line number
	mul		s2, t0, s3							// ICACHE size

#else
	li		t0, PA2VA(ADM5120_SWCTRL_BASE)
	lw		t1, CODE_REG(t0)

	li		t2, 0x1000			// Constant: 4K
	li		t3, 0x800			// Constant: 2K

	/*  Determine ICACHE size  */
	li		t4, CPU_ICACHE_2K_WAY
	move	s0, t2
	and		t4, t4, t1
	movn	s0, t3, t4
	
	li		t4, CPU_ICACHE_2WAY
	sll		t5, s0, 1
	and		t4, t4, t1
	movn	s0, t5, t4
	
	li		s1, CPU_CACHE_LINE_SIZE
	
	/*  Determine DCAHCE size  */
	li		t4, CPU_DCACHE_2K_WAY
	move	s2, t2
	and		t4, t4, t1
	movn	s2, t3, t4

	li		t4, CPU_DCACHE_2WAY
	sll		t5, s2, 1
	and		t4, t4, t1
	movn	s2, t5, t4
	
	li		s3, CPU_CACHE_LINE_SIZE
#endif

2:
	/*====  Invalidate ICACHE and DCACHE  ====*/
	mtc0	zero, CP0_TAGLO_REG
	mtc0	zero, CP0_TAGHI_REG
	li		t0, MEM_KSEG0_BASE
	
	beqz	s0, 4f
	nop									/* Branch delay slot */
	
	/*  Invalidate ICACHE  */
	addu	t1, t0, s0
	sll		s1, s1, 3
	subu	t1, t1, s1

	move	t2, t0
3:
	cache	ICACHE_INDEX_STORETAG, 0x00(t2)
	cache	ICACHE_INDEX_STORETAG, 0x10(t2)
	cache	ICACHE_INDEX_STORETAG, 0x20(t2)
	cache	ICACHE_INDEX_STORETAG, 0x30(t2)
	cache	ICACHE_INDEX_STORETAG, 0x40(t2)
	cache	ICACHE_INDEX_STORETAG, 0x50(t2)
	cache	ICACHE_INDEX_STORETAG, 0x60(t2)
	cache	ICACHE_INDEX_STORETAG, 0x70(t2)
	bne		t2, t1, 3b
	addu	t2, t2, s1					/* Branch delay slot */

4:	
	beqz	s2, 6f
	nop									/* Branch delay slot */
	/*  Invalidate DCACHE  */
	addu	t1, t0, s2
	sll		s3, s3, 3
	subu	t1, t1, s3

	move	t2, t0
5:
	cache	DCACHE_INDEX_STORETAG, 0x00(t2)
	cache	DCACHE_INDEX_STORETAG, 0x10(t2)
	cache	DCACHE_INDEX_STORETAG, 0x20(t2)
	cache	DCACHE_INDEX_STORETAG, 0x30(t2)
	cache	DCACHE_INDEX_STORETAG, 0x40(t2)
	cache	DCACHE_INDEX_STORETAG, 0x50(t2)
	cache	DCACHE_INDEX_STORETAG, 0x60(t2)
	cache	DCACHE_INDEX_STORETAG, 0x70(t2)
	bne		t2, t1, 5b
	addu	t2, t2, s3					/* Branch delay slot */

6:	
	jr		ra
	nop									/* Branch delay slot */
END(init_cache)
.set reorder


LEAF(init_mpmc_sram)
	.set noreorder
	/* Program Mem_control Register */

	/* PA2VA() adds MEM_KSEG1_BASE (0xA0000000) to an address   */
	/* ADM1520_SWCTRL_BASE defined as 0x12000000                */
	/* HWPF_5120_MEMCNTL_CFG defined as                         */
	/* HWPF_5120_SDRAMSIZE_CFG | HWPF_5120_SDRAM_CNTL           */
	/* | HWPF_5120_ROMSIZE_CFG                                  */
	/* a. SDRAM_SIZE_16MBYTES         003 (first chip)          */
	/* b. MEMCNTL_SDRAM1_EN           020                       */
	/* c. 4 << 8                      400                       */

	li		a0, PA2VA(ADM5120_SWCTRL_BASE)
	li 		t0, HWPF_5120_MEMCNTL_CFG				/* Known to work */
//	li 		t0, 0x00050404
	sw 		t0, Mem_control_REG(a0)

	/* ADM5120_MPMC_BASE defined as 0x11000000 */
	/* MPMC_SM_CONFIG1_REG offset is 0x220     */
	/* (which is MPMCStaticConfig[1])          */

	li		a1, PA2VA(ADM5120_MPMC_BASE)
	
	/*  Static memory bank0 init  */
	addi	a2, a1, MPMC_SM_CONFIG1_REG
	
	li		t0, SmemBank0_Config
	sw		t0, 0(a2)
	li		t1, SmemBank0_WaitWen
	sw		t1, 4(a2)
	li		t2, SmemBank0_WaitOen
	sw		t2, 8(a2)
	li		t3, SmemBank0_WaitRd
	sw		t3, 12(a2)
	li		t4, SmemBank0_WaitPage
	sw		t4, 16(a2)
	li		t5, SmemBank0_WaitWr
	sw		t5, 20(a2)
	li		t6, SmemBank0_WaitTurn
	sw		t6, 24(a2)
	
#if (HWPF_5120_SMEM1_EN == OPTION_ENABLE)
	/*  Static memory bank1 init  */
	addi	a2, a1, MPMC_SM_CONFIG0_REG
	
	li		t0, SmemBank1_Config
	sw		t0, 0(a2)
	li		t1, SmemBank1_WaitWen
	sw		t1, 4(a2)
	li		t2, SmemBank1_WaitOen
	sw		t2, 8(a2)
	li		t3, SmemBank1_WaitRd
	sw		t3, 12(a2)
	li		t4, SmemBank1_WaitPage
	sw		t4, 16(a2)
	li		t5, SmemBank1_WaitWr
	sw		t5, 20(a2)
	li		t6, SmemBank1_WaitTurn
	sw		t6, 24(a2)