nand_bootinit.s

Boot code for ADM5120 with serial console for Edimax router.

	move	t2, t0
5:
	cache	DCACHE_INDEX_STORETAG, 0x00(t2)
	cache	DCACHE_INDEX_STORETAG, 0x10(t2)
	cache	DCACHE_INDEX_STORETAG, 0x20(t2)
	cache	DCACHE_INDEX_STORETAG, 0x30(t2)
	cache	DCACHE_INDEX_STORETAG, 0x40(t2)
	cache	DCACHE_INDEX_STORETAG, 0x50(t2)
	cache	DCACHE_INDEX_STORETAG, 0x60(t2)
	cache	DCACHE_INDEX_STORETAG, 0x70(t2)
	bne		t2, t1, 5b
	addu	t2, t2, s3					/* Branch delay slot */

6:	
	jr		ra
	nop									/* Branch delay slot */
END(init_cache)
.set reorder

LEAF(init_mpmc_sdram)
	/* Program Mem_control Register */

	li		a0, PA2VA(ADM5120_SWCTRL_BASE)
	li		a1, PA2VA(ADM5120_MPMC_BASE)

	/*====  SDRAM init  ====*/
	/* Make sure the the address mirror is off*/
	lw		t0, MPMC_CONTROL_REG(a1)
	li		t1, ~MPMC_ADDR_MIRROR	
	and		t0, t0, t1
	sw		t0,  MPMC_CONTROL_REG(a1)

	/*  Set SDRAM accessing timing  */	
	addi	a2, a1, MPMC_DM_TRP_REG

	li		t0, HWPF_5120_SDRAM_tRP
	sw		t0, 0(a2)
	li		t1, HWPF_5120_SDRAM_tRAS
	sw		t1, 4(a2)
	li		t2, HWPF_5120_SDRAM_tSREX
	sw		t2, 8(a2)
	li		t3, HWPF_5120_SDRAM_tAPR
	sw		t3, 12(a2)
	li		t4, HWPF_5120_SDRAM_tDAL
	sw		t4, 16(a2)
	li		t5, HWPF_5120_SDRAM_tWR
	sw		t5, 20(a2)
	li		t6, HWPF_5120_SDRAM_tRC
	sw		t6, 24(a2)
	li		t7, HWPF_5120_SDRAM_tRFC
	sw		t7, 28(a2)
	li		t8, HWPF_5120_SDRAM_tXSR
	sw		t8, 32(a2)
	li		t9, HWPF_5120_SDRAM_tRRD
	sw		t9, 36(a2)
	li		s0, HWPF_5120_SDRAM_tMRD
	sw		s0, 40(a2)
	
	
	/* Get MPMC_DM_CONTROL_REG */
	lw		s0, MPMC_DM_CONTROL_REG(a1)
	li		t1, ~DM_SDRAM_OPMODE_MASK
	and		s0, s0, t1
	
	// Make sure CLK ENABLE is HIGH during the initializing process
	or		t0, s0, (DM_CLKEN_ALWAYS|DM_CLKOUT_ALWAYS)
	sw		t0, MPMC_DM_CONTROL_REG(a1)

	// Turn off SDRAM0 buffer of all banks
	lw		t0, MPMC_DM_CONFIG0_REG(a1)
	li		t1, ~DM_CFG_BUFFER_EN
	and		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG0_REG(a1)
	
#if HWPF_5120_SDRAM_BANK_NUM == 2
	// Turn off SDRAM1 buffer of all banks
	lw		t0, MPMC_DM_CONFIG1_REG(a1)
//	li		t1, ~DM_CFG_BUFFER_EN
	and		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG1_REG(a1)
#endif	
	
#ifndef RTL_SIMULATION
	// Prepare some constant
	li		t5, SW_TIMER_100US_TICKS
	li		t6, (SW_TIMER_INT_DISABLE | SW_TIMER_INT)
	li		t7, 0xffff
    li		t8, SW_TIMER_EN
#endif

	/*  wait at leaset 1ms until SDRAMs power and clocks stabilized.  */
#ifndef RTL_SIMULATION
	/* stop timer */
	sw		t7, Timer_REG(a0)
	/* clear timer interrupt status bit */ 
	sw		t6, Timer_int_REG(a0)

	/* Start timer to count 1.6 ms */
	sll		t0, t5, 4				/*  100us * 2^4 */
	or		t0, t0, t8
	sw		t0, Timer_REG(a0)
	
1:
	lw		t1, Timer_int_REG(a0)
	and		t0, t1, SW_TIMER_INT
	beqz	t0, 1b
	
#else

	li		t0, 0x10
1:
	nop
	nop        
	subu 	t0, t0, 1
	bnez	t0, 1b
#endif

	/* Issue NOP command to ALL SDRAM. */
	or		t0, s0, DM_SDRAM_NOP
	sw		t0, MPMC_DM_CONTROL_REG(a1)

	/*  wait at least 200us  */
#ifndef RTL_SIMULATION
	/* stop timer */
	sw		t7, Timer_REG(a0)
	/* clear timer interrupt status bit */ 
	sw		t6, Timer_int_REG(a0)

	/* Start timer to count 200us */
	sll		t0, t5, 1				/*  100us * 2^1		*/
	or		t0, t0, t8
	sw		t0, Timer_REG(a0)
	
1:
	lw		t1, Timer_int_REG(a0)
	and		t0, t1, SW_TIMER_INT
	beqz	t0, 1b
#else
	li		t0, 0x20
1:
	nop
	nop
	subu 	t0, t0, 1
	bnez	t0, 1b
#endif

	/* Issues PRE-ALL to ALL SDRAM  */
	or		t0, s0, DM_SDRAM_PRECHARGE_ALL
	sw		t0, MPMC_DM_CONTROL_REG(a1)

	/* Write 2 to refresh timier.
	 * The memory controller will issue refresh every 32 sdram clocks. 
	 */
	li		t0, 2
	sw		t0, MPMC_DM_REFRESH_REG(a1)

	/* wait at least 8 refresh cycle (32*8=256 sdram clock or 512 CPU clock) */
	li		t0, 64
1:
	nop							/*	1	*/
	nop        					/*	2	*/
	nop							/*	3	*/
	nop        					/*	4	*/
	nop							/*	5	*/
	subu 	t0, t0, 1			/*	6	*/
	bnez	t0, 1b				/* 7,8	*/

	/* Set refresh timer to normal operation value  */
	li		t0, HWPF_5120_SDRAM_RFTIME
	sw		t0, MPMC_DM_REFRESH_REG(a1)

	/* Program the RAS/CAS value of SDRAM bank 0 */
	li		t0, SDRAM_BANK0_RAS_CAS
	sw		t0, MPMC_DM_RASCAS0_REG(a1)
	
	/* Program the configuration of SDRAM bank 0 */
	li		t0, MPMC_SDRAM_BANK0_CFG
	// make sure that the read/write buffer is disabled
	li		t1, ~DM_CFG_BUFFER_EN
	and		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG0_REG(a1)

#if HWPF_5120_SDRAM_BANK_NUM == 2
	/* Program the RAS/CAS value of SDRAM bank 1 */
	li 		t0, SDRAM_BANK1_RAS_CAS
	sw		t0, MPMC_DM_RASCAS1_REG(a1)
	
	/* Program the configuration of SDRAM bank 1 */
	li		t0, MPMC_SDRAM_BANK1_CFG
	// make sure that the read/write buffer is disabled
	and		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG1_REG(a1)
#endif	// ! HWPF_5120_SDRAM_BANK_NUM == 2

	/****  Program the mode register in SDRAM  ****/	
	// MPMC sdram mode setting 
	or		t0, s0, DM_SDRAM_MODE_SETTING
	sw		t0, MPMC_DM_CONTROL_REG(a1)
	
	/* Program the mode register of SDRAM bank0*/
	li		t0, PA2VA(HWPF_5120_SDRAM0_BASE)
	li		t1, SDRAM_BANK0_MODE
	sll		t1, t1, SDRAM_BANK0_MODE_SHIFT
	add		t0, t1, t0
	lw		t1, 0(t0)


#if HWPF_5120_SDRAM_BANK_NUM == 2
	/* Program the mode register of SDRAM bank1*/
	li		t0, PA2VA(HWPF_5120_SDRAM1_BASE)
	li		t1, SDRAM_BANK1_MODE
	sll		t1, t1, SDRAM_BANK1_MODE_SHIFT
	add		t0, t1, t0
	lw		t1, 0(t0)
#endif	// ! HWPF_5120_SDRAM_BANK_NUM == 2
	
	// SDRAM is ready now, put it to normal operation mode
	or		t0, s0, DM_SDRAM_NORMAL_OP
	
	// Clear DM_CLKEN_ALWAYS bit
	li		t1, ~DM_CLKEN_ALWAYS
	and		t0, t0, t1
	sw		t0, MPMC_DM_CONTROL_REG(a1)
	
	// Enable the Read/Write buffers of SDRAM banks0
	lw 		t0, MPMC_DM_CONFIG0_REG(a1)
	li		t1, DM_CFG_BUFFER_EN
	or		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG0_REG(a1)

#if HWPF_5120_SDRAM_BANK_NUM == 2
	// Enable the Read/Write buffers of SDRAM banks1
	lw 		t0, MPMC_DM_CONFIG1_REG(a1)
	or		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG1_REG(a1)
#endif  // ! HWPF_5120_SDRAM_BANK_NUM == 2

	jr		ra
END(init_mpmc_sdram)

/* 
 *  copy image from NAND flash to SDRAM
 *	
 */
LEAF(img_copy)

	li		s0, RUNTIME_START_PAGE				//starting page
	li		s1, RUNTIME_IMG_ADDR				//destination address
	li		s2,	RUNTIME_PAGE_TOTAL				//page number

	// reserve the returned address
	move	s3, ra

	li		t0, PA2VA(ADM5120_SMEM1_BASE)
	li		t1, NAND_SET_BIT
	
1:
	/* Clear the CE pin to low */
	sb		t1, NAND_CLR_CE_REG(t0)

	/* Set the CLE pin to high */
	sb		t1, NAND_SET_CLE_REG(t0)

	/* Read data command */
	sb		zero, NAND_RW_REG(t0)

	/* Clear the CLE pint to low */
	sb		t1, NAND_CLR_CLE_REG(t0)

	/* Set the ALE pint to high */
	sb		t1, NAND_SET_ALE_REG(t0)

	/* Init starting address */
	li		t2, NAND_FLASH_PAGE_SIZE
	mul		t2, t2, s0
	
	/* Set starting address 1: bit [a7:a0] */
	//and		t3, t2, NAND_ADDR1_MASK 
	sb		zero, NAND_RW_REG(t0)

	/* Set starting address 2: bit [a16:a9] */
	//and		t3, t2, NAND_ADDR2_MASK
	srl		t3, t2, 9
	and		t3, t3, NAND_ADDR2_MASK
	sb		t3, NAND_RW_REG(t0)

	/* Set starting address 3: bit [a22:a17] */
	//and		t3, t2, NAND_ADDR3_MASK
	srl		t3, t2, 17
	and		t3, t3, NAND_ADDR3_MASK
	sb		t3, NAND_RW_REG(t0)

	/* Clear the ALE pin to low */
	sb		t1, NAND_CLR_ALE_REG(t0)

	/* Wait 100 us */
	li		a0, 1
	bal		wait_tick
	nop

	/* Copy loop */
	li		t2, NAND_FLASH_PAGE_SIZE	/* data length */

2:
	lb		t3, NAND_RW_REG(t0)
	sb		t3, (s1)
	add		s1, 1
	subu	t2, 1
	bnez	t2, 2b
	nop

	/* Set the ALE pin to high */
	sb		t1, NAND_SET_CE_REG(t0)

	add		s0, 1
	subu	s2, 1
	bnez	s2, 1b
	nop

	jr		s3
	nop

END(img_copy)
/* 
 *  wait n  * 100us
 *	input : a0 - wait ticks
 */
LEAF(wait_tick)

	li		t4, PA2VA(ADM5120_SWCTRL_BASE)

	li		t5, SW_TIMER_100US_TICKS
	li		t6, (SW_TIMER_INT_DISABLE | SW_TIMER_INT)
	li		t7, 0xffff
    li		t8, SW_TIMER_EN

	/* stop timer */
	sw		t7, Timer_REG(t4)

	/* clear timer interrupt status bit */ 
	sw		t5, Timer_int_REG(t4)

	/* Start timer to count n * 100us */
	mul		t9, t5, a0
	or		t9, t9, t8
	sw		t9, Timer_REG(t4)
	
1:
	lw		t5, Timer_int_REG(t4)
	and		t6, t5, SW_TIMER_INT
	beqz	t6, 1b
	nop

	jr		ra
	nop

END(wait_tick)