nand_bootinit.s

Boot code for ADM5120 with serial console for Edimax router.

/*****************************************************************************
;
;   (C) Unpublished Work of ADMtek Incorporated.  All Rights Reserved.
;
;       THIS WORK IS AN UNPUBLISHED WORK AND CONTAINS CONFIDENTIAL,
;       PROPRIETARY AND TRADESECRET INFORMATION OF ADMTEK INCORPORATED.
;       ACCESS TO THIS WORK IS RESTRICTED TO (I) ADMTEK EMPLOYEES WHO HAVE A
;       NEED TO KNOW TO PERFORM TASKS WITHIN THE SCOPE OF THEIR ASSIGNMENTS
;       AND (II) ENTITIES OTHER THAN ADMTEK WHO HAVE ENTERED INTO APPROPRIATE
;       LICENSE AGREEMENTS.  NO PART OF THIS WORK MAY BE USED, PRACTICED,
;       PERFORMED, COPIED, DISTRIBUTED, REVISED, MODIFIED, TRANSLATED,
;       ABBRIDGED, CONDENSED, EXPANDED, COLLECTED, COMPILED, LINKED, RECAST,
;       TRANSFORMED OR ADAPTED WITHOUT THE PRIOR WRITTEN CONSENT OF ADMTEK.
;       ANY USE OR EXPLOITATION OF THIS WORK WITHOUT AUTHORIZATION COULD
;       SUBJECT THE PERPERTRATOR TO CRIMINAL AND CIVIL LIABILITY.
;
;------------------------------------------------------------------------------
;
;    Project : ADM5120
;    Creator : 
;    File    : bootinit.S
;    Abstract: 
;
;Modification History:
; 
;
;*****************************************************************************/


#include <mips.h>
#include <mips4kc.h>
#include <asm.h>
#include <adm5120.h>
#include <hw5120cfg.h>

#define NAND_BOOT
#define NAND_FLASH_PAGE_SIZE	512
#define NAND_ADD1_MASK		0xff
#define NAND_ADDR2_MASK		0xff
#define NAND_ADDR3_MASK		0x3f

#define RUNTIME_START_PAGE	8
#define RUNTIME_IMG_ADDR	0x80801000
#define RUNTIME_PAGE_TOTAL	0x100

.set noreorder
.set noat

.text
.org 0
VECTOR(_nand_reset, unknown)
	/* Read current status */
	mfc0 	k0, CP0_STATUS_REG
	
	/* Is this a NMI */
	li		k1, CP0_STATUS_NMI_BIT
	and		k1, k0, k1
	beqz	k1, 2f						/* Branch if this is not a NMI. */
	nop									/* Branch delay slot */

1:
	b		1b
	nop
	
2:
	/*  Cold boot or Software reset  */

	/*=====  Initialize CP0 register  ====*/
	/* Set IV bit */	
	li 		t0, CP0_CAUSE_IV_BIT
	mtc0	t0, CP0_CAUSE_REG
	
	/* Clear watch register */	
	mtc0	zero, CP0_WATCHLO_REG
	mtc0	zero, CP0_WATCHHI_REG
	
	/* Set status register */
	li 		t0, CP0_STATUS_DEFAULT
	mtc0	t0, CP0_STATUS_REG
	
	/* Set configure 0 register */
	li 		t0, CP0_CONFIG0_DEFAULT
	mtc0	t0, CP0_CONFIG0_REG

	bal		init_mpmc_sram
	nop

#ifndef KSEG0_UNCACHED
	// Init cache
	bal		_C_LABEL(init_cache)
	nop									/* Branch delay slot */
#endif
	
	/*  In KSEG0, cached  */
	bal		init_mpmc_sdram
	nop
	
	/*===== Copy Switch temporary buffer to SDRAM =====*/
	/*  Disable interrupt  */
	mfc0	v0, CP0_STATUS_REG
	and	v0, CP0_STATUS_BEV_BIT
	mtc0	v0, CP0_STATUS_REG

	/*  Get current position  */
	bal		_C_LABEL(_get_pc)
	nop

	/*  v0 now hold the run time address of _mark1  */
_mark1:
	move	a0, v0

	la		a1, _C_LABEL(_nand_reset)		// a1 holds the start address of nandreset in DRAM
	la		t0, _C_LABEL(_mark1)
	
	/*  Calculate the offset from nandreset to _mark1  */
	subu	t0, t0, a1		// t0 holds the length from nandreset to _mark1
	subu	a0, a0, t0		// a0 holds the start address of nandreset in rom
	move	s0, a0
	li		a2, 0x800		// a2 holds the length of the program
	
	/*
	 *  Copy the program code from rom to SDRAM
	 *		a0 : Source address of program image in ROM
	 *		a1 : Destination address
	 *		a2 : length of program image
	 */
	 
	/*  Copy code loop  */
1:
	lw		t0, 0(a0)
	subu	a2, a2, 4*4			// substract the length to be copied
	lw		t1, 4(a0)
	sw		t0, 0(a1)
	lw		t2, 8(a0)	
	sw		t1, 4(a1)
	lw		t3, 12(a0)
	sw		t2, 8(a1)
	addu	a0, a0, 4*4			// next source address
	sw		t3, 12(a1)
	addu	a1, a1, 4*4			//next destination address
	cache	ICACHE_HIT_INVALIDATE, 0(a1)
	bgtz	a2, 1b
	nop

	// Jump to SDRAM 
	la		t0, 2f				
	jr		t0
	nop
2:		
	/* enable nand flash */
	li		t0, 0xb1000200
	li		t1, 0x80
	sw		t1, 0(t0)
	li		t0, PA2VA(ADM5120_SWCTRL_BASE)
	li		t1, NAND_ENABLE
	sw		t1, BW_cntl1_REG(t0)
	
	/* Set boot done */
	li		t1, 0x01
	sw		t1, MPMC_CONFIG_REG(t0)
	
	/* Move runtime image to sdram */
	bal		img_copy
	nop

	/* jump to the entry point of the runtime code */
	li		t0, RUNTIME_IMG_ADDR
	jr		t0
	nop
	
	/* Not reached here */
3:	
	b		3b
	nop									/* Branch delay slot */
VECTOR_END(_nand_reset)

VECTOR(init_mpmc_sram, unknown)
	/* Program Mem_control Register */

	li		a0, PA2VA(ADM5120_SWCTRL_BASE)
	li 		t0, HWPF_5120_MEMCNTL_CFG
	sw 		t0, Mem_control_REG(a0)

	li		a1, PA2VA(ADM5120_MPMC_BASE)
	
	/*  Static memory bank0 init  */
	addi	a2, a1, MPMC_SM_CONFIG1_REG
	
#ifdef NAND_BOOT
	li		t0, 0x80
#else
	li		t0, SmemBank0_Config
#endif
	sw		t0, 0(a2)
	li		t1, SmemBank0_WaitWen
	sw		t1, 4(a2)
	li		t2, SmemBank0_WaitOen
	sw		t2, 8(a2)
	li		t3, SmemBank0_WaitRd
	sw		t3, 12(a2)
	li		t4, SmemBank0_WaitPage
	sw		t4, 16(a2)
	li		t5, SmemBank0_WaitWr
	sw		t5, 20(a2)
	li		t6, SmemBank0_WaitTurn
	sw		t6, 24(a2)
#if (HWPF_5120_SMEM1_EN == OPTION_ENABLE)
	/*  Static memory bank1 init  */
	addi	a2, a1, MPMC_SM_CONFIG0_REG
	
	li		t0, SmemBank1_Config
	sw		t0, 0(a2)
	li		t1, SmemBank1_WaitWen
	sw		t1, 4(a2)
	li		t2, SmemBank1_WaitOen
	sw		t2, 8(a2)
	li		t3, SmemBank1_WaitRd
	sw		t3, 12(a2)
	li		t4, SmemBank1_WaitPage
	sw		t4, 16(a2)
	li		t5, SmemBank1_WaitWr
	sw		t5, 20(a2)
	li		t6, SmemBank1_WaitTurn
	sw		t6, 24(a2)
#endif	

	jr		ra
	
VECTOR_END(init_mpmc_sram)

LEAF(_get_pc)
	move	v0, ra
	jr		ra
END(_get_pc)

.set noreorder
LEAF(init_cache)
	/*====  Initialize Cache  ====*/

	/* Read cache configuration  */
#if 1
	mfc0	a0, CP0_CONFIG1_REG, CP0_CONFIG1_SEL

	/*  Determine ICACHE size  */
	li		t0, CP0_CONFIG1_IL_MASK
	and		t0, t0, a0
	srl		t0, t0, CP0_CONFIG1_IL_SHIFT
	
	beqz	t0, 1f
	li		s0, 0								/* Branch delay slot */
	// ICACHE line size is 16 bytes
	li		s1, 0x10

	li		t0, CP0_CONFIG1_IS_MASK
	and		t0, t0, a0
	srl		t0, t0, CP0_CONFIG1_IS_SHIFT
	li		t1, 64
	sll		t1, t1, t0							// lines per way
	
	li		t0, CP0_CONFIG1_IA_MASK	
	and		t2, t0, a0
	srl		t2, t2, CP0_CONFIG1_IA_SHIFT
	addiu	t2, t2, 1							// Number of way

	mul		t0, t1, t2							// total ICACHE line number
	mul		s0, t0, s1							// ICACHE size

1:
	/*  Determine DCACHE size  */
	li		t0, CP0_CONFIG1_DL_MASK
	and		t0, t0, a0
	srl		t0, t0, CP0_CONFIG1_DL_SHIFT
	
	beqz	t0, 2f
	li		s2, 0								/* Branch delay slot */
	// DCACHE line size is 16 bytes
	li		s3, 0x10

	li		t0, CP0_CONFIG1_DS_MASK
	and		t0, t0, a0
	srl		t0, t0, CP0_CONFIG1_DS_SHIFT
	li		t1, 64
	sll		t1, t1, t0							// lines per way

	li		t0, CP0_CONFIG1_DA_MASK	
	and		t2, t0, a0
	srl		t2, t2, CP0_CONFIG1_DA_SHIFT
	addiu	t2, t2, 1							// Number of way

	mul		t0, t1, t2							// total ICACHE line number
	mul		s2, t0, s3							// ICACHE size

#else
	li		t0, PA2VA(ADM5120_SWCTRL_BASE)
	lw		t1, CODE_REG(t0)

	li		t2, 0x1000			// Constant: 4K
	li		t3, 0x800			// Constant: 2K

	/*  Determine ICACHE size  */
	li		t4, CPU_ICACHE_2K_WAY
	move	s0, t2
	and		t4, t4, t1
	movn	s0, t3, t4
	
	li		t4, CPU_ICACHE_2WAY
	sll		t5, s0, 1
	and		t4, t4, t1
	movn	s0, t5, t4
	
	li		s1, CPU_CACHE_LINE_SIZE
	
	/*  Determine DCAHCE size  */
	li		t4, CPU_DCACHE_2K_WAY
	move	s2, t2
	and		t4, t4, t1
	movn	s2, t3, t4

	li		t4, CPU_DCACHE_2WAY
	sll		t5, s2, 1
	and		t4, t4, t1
	movn	s2, t5, t4
	
	li		s3, CPU_CACHE_LINE_SIZE
#endif

2:
	/*====  Invalidate ICACHE and DCACHE  ====*/
	mtc0	zero, CP0_TAGLO_REG
	mtc0	zero, CP0_TAGHI_REG
	li		t0, MEM_KSEG0_BASE
	
	beqz	s0, 4f
	nop									/* Branch delay slot */
	
	/*  Invalidate ICACHE  */
	addu	t1, t0, s0
	sll		s1, s1, 3
	subu	t1, t1, s1

	move	t2, t0
3:
	cache	ICACHE_INDEX_STORETAG, 0x00(t2)
	cache	ICACHE_INDEX_STORETAG, 0x10(t2)
	cache	ICACHE_INDEX_STORETAG, 0x20(t2)
	cache	ICACHE_INDEX_STORETAG, 0x30(t2)
	cache	ICACHE_INDEX_STORETAG, 0x40(t2)
	cache	ICACHE_INDEX_STORETAG, 0x50(t2)
	cache	ICACHE_INDEX_STORETAG, 0x60(t2)
	cache	ICACHE_INDEX_STORETAG, 0x70(t2)
	bne		t2, t1, 3b
	addu	t2, t2, s1					/* Branch delay slot */

4:	
	beqz	s2, 6f
	nop									/* Branch delay slot */
	/*  Invalidate DCACHE  */
	addu	t1, t0, s2
	sll		s3, s3, 3
	subu	t1, t1, s3