nor_bootmod.s

Boot code for ADM5120 with serial console for Edimax router.

/*****************************************************************************
;
;	TEST of modified boot loader
;
;------------------------------------------------------------------------------
;
;    Project : ADM5120
;    Creator : Dan Everett
;    File    : bootmod.S
;
;*****************************************************************************/

#include <mips.h>
#include <mips4kc.h>
#include <asm.h>
#include <adm5120.h>
#include <hw5120cfg.h>

/* Instead of the normal bootloader init done from the romreset_except */
/* vector (as in nor_bootinit.S), we're starting in KSEG0 where the    */
/* real bootloader thinks it's transferring control to Linux.          */
/* See entry point _modinit which is NOT at the start of this file.    */

#include <test_def.h>

.text

.set noreorder

LEAF(init_cache)
	/* === Re-Initialize Cache ===*/

	/* Read cache configuration */

	mfc0	a0, CP0_CONFIG1_REG, CP0_CONFIG1_SEL

	/* Determine ICACHE size */
	li		t0, CP0_CONFIG1_IL_MASK
	and		t0, t0, a0
	srl		t0, t0, CP0_CONFIG1_IL_SHIFT
	beqz	t0, 1f
	li		s0, 0

	/* ICACHE line size is 16 bytes */
	li		s1, 16
	li		t0, CP0_CONFIG1_IS_MASK
	and		t0, t0, a0
	srl		t0, t0, CP0_CONFIG1_IS_SHIFT
	li		t1, 64
	sll		t1, t1, t0

	li		t0, CP0_CONFIG1_IA_MASK
	and		t2, t0, a0
	srl		t2, t2, CP0_CONFIG1_IA_SHIFT
	addiu	t2, t2, 1

	mul		t0, t1, t2
	mul		s0, t0, s1

1:
	/* Determine DCACHE size */
	li		t0, CP0_CONFIG1_DL_MASK
	and		t0, t0, a0
	srl		t0, t0, CP0_CONFIG1_DL_SHIFT
	beqz	t0, 2f
	li		s2, 0

	/* DCACHE line size is 16 bytes */
	li		s3, 16
	li		t0, CP0_CONFIG1_DS_MASK
	and		t0, t0, a0
	srl		t0, t0, CP0_CONFIG1_DS_SHIFT
	li		t1, 64
	sll		t1, t1, t0

	li		t0, CP0_CONFIG1_DA_MASK
	and		t2, t0, a0
	srl		t2, t2, CP0_CONFIG1_DA_SHIFT
	addiu	t2, t2, 1

	mul		t0, t1, t2
	mul		s2, t0, s3

2:
	/*=== Invalidate ICACHE and DCACHE ===*/
	mtc0	zero, CP0_TAGLO_REG
	mtc0	zero, CP0_TAGHI_REG
	li		t0, MEM_KSEG0_BASE

	beqz	s0, 4f
	nop

	/* Invalidate ICACHE */
	addu	t1, t0, s0
	sll		s1, s1, 3
	subu	t1, t1, s1

	move	t2, t0
3:
	cache	ICACHE_INDEX_STORETAG, 0x00(t2)
	cache	ICACHE_INDEX_STORETAG, 0x10(t2)
	cache	ICACHE_INDEX_STORETAG, 0x20(t2)
	cache	ICACHE_INDEX_STORETAG, 0x30(t2)
	cache	ICACHE_INDEX_STORETAG, 0x40(t2)
	cache	ICACHE_INDEX_STORETAG, 0x50(t2)
	cache	ICACHE_INDEX_STORETAG, 0x60(t2)
	cache	ICACHE_INDEX_STORETAG, 0x70(t2)
	bne		t2, t1, 3b
	addu	t2, t2, s1

4:
	beqz	s2, 6f
	nop

	/* Invalidate DCACHE */
	addu	t1, t0, s2
	sll		s3, s3, 3
	subu	t1, t1, s3

	move	t2, t0
5:
	cache	DCACHE_INDEX_STORETAG, 0x00(t2)
	cache	DCACHE_INDEX_STORETAG, 0x10(t2)
	cache	DCACHE_INDEX_STORETAG, 0x20(t2)
	cache	DCACHE_INDEX_STORETAG, 0x30(t2)
	cache	DCACHE_INDEX_STORETAG, 0x40(t2)
	cache	DCACHE_INDEX_STORETAG, 0x50(t2)
	cache	DCACHE_INDEX_STORETAG, 0x60(t2)
	cache	DCACHE_INDEX_STORETAG, 0x70(t2)
	bne		t2, t1, 5b
	addu	t2, t2, s3

6:
	jr		ra
	nop
END(init_cache)


LEAF(init_mpmc_sram)
	/* Program Mem_control Register */

	/* PA2VA() adds MEM_KSEG1_BASE (0xA0000000) to an address   */
	/* ADM1520_SWCTRL_BASE defined as 0x12000000                */
	/* HWPF_5120_MEMCNTL_CFG defined as                         */
	/* HWPF_5120_SDRAMSIZE_CFG | HWPF_5120_SDRAM_CNTL           */
	/* | HWPF_5120_ROMSIZE_CFG                                  */
	/* a. SDRAM_SIZE_16MBYTES         003 (first chip)          */
	/* b. MEMCNTL_SDRAM1_EN           020                       */
	/* c. 4 << 8                      400                       */

	li		a0, PA2VA(ADM5120_SWCTRL_BASE)

	/* Set parameters for SRAM (NOR Flash) and SDRAM */
	li 		t0, HWPF_5120_MEMCNTL_CFG
	sw 		t0, Mem_control_REG(a0)

	/* ADM5120_MPMC_BASE defined as 0x11000000 */
	/* MPMC_SM_CONFIG1_REG offset is 0x220     */
	/* (which is MPMCStaticConfig[1])          */

	li		a1, PA2VA(ADM5120_MPMC_BASE)

	/*  Static memory bank0 init  */
	addi	a2, a1, MPMC_SM_CONFIG1_REG

	li		t0, SmemBank0_Config
	sw		t0, 0(a2)
	li		t1, SmemBank0_WaitWen
	sw		t1, 4(a2)
	li		t2, SmemBank0_WaitOen
	sw		t2, 8(a2)
	li		t3, SmemBank0_WaitRd
	sw		t3, 12(a2)
	li		t4, SmemBank0_WaitPage
	sw		t4, 16(a2)
	li		t5, SmemBank0_WaitWr
	sw		t5, 20(a2)
	li		t6, SmemBank0_WaitTurn
	sw		t6, 24(a2)

#if (HWPF_5120_SMEM1_EN == OPTION_ENABLE)
	/*  Static memory bank1 init  */
	addi	a2, a1, MPMC_SM_CONFIG0_REG

	li		t0, SmemBank1_Config
	sw		t0, 0(a2)
	li		t1, SmemBank1_WaitWen
	sw		t1, 4(a2)
	li		t2, SmemBank1_WaitOen
	sw		t2, 8(a2)
	li		t3, SmemBank1_WaitRd
	sw		t3, 12(a2)
	li		t4, SmemBank1_WaitPage
	sw		t4, 16(a2)
	li		t5, SmemBank1_WaitWr
	sw		t5, 20(a2)
	li		t6, SmemBank1_WaitTurn
	sw		t6, 24(a2)
#endif	

	jr		ra
	nop
END(init_mpmc_sram)

LEAF(init_mpmc_sdram)
	/* Program Mem_control Register */

	/* Make sure the the address mirror is off*/
	li		a0, PA2VA(ADM5120_SWCTRL_BASE)
	li		a1, PA2VA(ADM5120_MPMC_BASE)

	lw		t0, MPMC_CONTROL_REG(a1)
	li		t1, ~MPMC_ADDR_MIRROR	
	and		t0, t0, t1
	sw		t0,  MPMC_CONTROL_REG(a1)

	/*  Set SDRAM accessing timing  */	
	addi	a2, a1, MPMC_DM_TRP_REG

	li		t0, HWPF_5120_SDRAM_tRP
	sw		t0, 0(a2)
	li		t1, HWPF_5120_SDRAM_tRAS
	sw		t1, 4(a2)
	li		t2, HWPF_5120_SDRAM_tSREX
	sw		t2, 8(a2)
	li		t3, HWPF_5120_SDRAM_tAPR
	sw		t3, 12(a2)
	li		t4, HWPF_5120_SDRAM_tDAL
	sw		t4, 16(a2)
	li		t5, HWPF_5120_SDRAM_tWR
	sw		t5, 20(a2)
	li		t6, HWPF_5120_SDRAM_tRC
	sw		t6, 24(a2)
	li		t7, HWPF_5120_SDRAM_tRFC
	sw		t7, 28(a2)
	li		t8, HWPF_5120_SDRAM_tXSR
	sw		t8, 32(a2)
	li		t9, HWPF_5120_SDRAM_tRRD
	sw		t9, 36(a2)
	li		s0, HWPF_5120_SDRAM_tMRD
	sw		s0, 40(a2)

	/* Get MPMC_DM_CONTROL_REG */
	lw		s0, MPMC_DM_CONTROL_REG(a1)
	li		t1, ~DM_SDRAM_OPMODE_MASK
	and		s0, s0, t1

	/* Make sure CLK ENABLE is HIGH during the initializing process */
	or		t0, s0, (DM_CLKEN_ALWAYS|DM_CLKOUT_ALWAYS)
	sw		t0, MPMC_DM_CONTROL_REG(a1)

	/* Turn off SDRAM0 buffer of all banks */
	lw		t0, MPMC_DM_CONFIG0_REG(a1)
	li		t1, ~DM_CFG_BUFFER_EN
	and		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG0_REG(a1)

#if HWPF_5120_SDRAM_BANK_NUM == 2
	/* Turn off SDRAM1 buffer of all banks */
	lw		t0, MPMC_DM_CONFIG1_REG(a1)
	and		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG1_REG(a1)
#endif	

	/* Prepare some constants */
	li		t5, SW_TIMER_100US_TICKS
	li		t6, (SW_TIMER_INT_DISABLE | SW_TIMER_INT)
	li		t7, 0xffff
    li		t8, SW_TIMER_EN

	/*  Wait at leaset 1ms until SDRAMs power and clocks stabilize */
	sw		t7, Timer_REG(a0)

	/* Clear timer interrupt status bit */
	sw		t6, Timer_int_REG(a0)

	/* Start timer to count 1.6 ms */
	sll		t0, t5, 4
	or		t0, t0, t8
	sw		t0, Timer_REG(a0)

1:
	lw		t1, Timer_int_REG(a0)
	and		t0, t1, SW_TIMER_INT
	beqz	t0, 1b
	nop

	/* Issue NOP command to ALL SDRAM. */
	or		t0, s0, DM_SDRAM_NOP
	sw		t0, MPMC_DM_CONTROL_REG(a1)

	/* Wait at least 200us  */
	sw		t7, Timer_REG(a0)

	/* clear timer interrupt status bit */
	sw		t6, Timer_int_REG(a0)

	/* Start timer to count 200us */
	sll		t0, t5, 1
	or		t0, t0, t8
	sw		t0, Timer_REG(a0)

1:
	lw		t1, Timer_int_REG(a0)
	and		t0, t1, SW_TIMER_INT
	beqz	t0, 1b
	nop

	/* Issues PRE-ALL to ALL SDRAM  */
	or		t0, s0, DM_SDRAM_PRECHARGE_ALL
	sw		t0, MPMC_DM_CONTROL_REG(a1)

	/* Write 2 to refresh timier so that the memory controller */
	/* will issue refresh every 32 sdram clocks                */
	li		t0, 2
	sw		t0, MPMC_DM_REFRESH_REG(a1)

	/* Wait at least 8 refresh cycle (32*8=256 sdram clock or 512 CPU clock) */
	li		t0, 64
1:
	nop							/*	1	*/
	nop        					/*	2	*/
	nop							/*	3	*/
	nop        					/*	4	*/
	nop							/*	5	*/
	subu 	t0, t0, 1			/*	6	*/
	bnez	t0, 1b				/* 7,8	*/
	nop

	/* Set refresh timer to normal operation value */
	li		t0, HWPF_5120_SDRAM_RFTIME
	sw		t0, MPMC_DM_REFRESH_REG(a1)

	/* Program the RAS/CAS value of SDRAM bank 0 */
	li		t0, SDRAM_BANK0_RAS_CAS
	sw		t0, MPMC_DM_RASCAS0_REG(a1)

	/* Program the configuration of SDRAM bank 0 */
	li		t0, MPMC_SDRAM_BANK0_CFG

	/* Make sure that the read/write buffer is disabled */
	li		t1, ~DM_CFG_BUFFER_EN
	and		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG0_REG(a1)

#if HWPF_5120_SDRAM_BANK_NUM == 2
	/* Program the RAS/CAS value of SDRAM bank 1 */
	li 		t0, SDRAM_BANK1_RAS_CAS
	sw		t0, MPMC_DM_RASCAS1_REG(a1)
	
	/* Program the configuration of SDRAM bank 1 */
	li		t0, MPMC_SDRAM_BANK1_CFG
	// make sure that the read/write buffer is disabled
	and		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG1_REG(a1)
#endif	// ! HWPF_5120_SDRAM_BANK_NUM == 2

	/* Program the mode register in SDRAM */
	/* Set the MPMC SDRAM mode            */
	or		t0, s0, DM_SDRAM_MODE_SETTING
	sw		t0, MPMC_DM_CONTROL_REG(a1)

	/* Program the mode register of SDRAM bank0 */
	li		t0, PA2VA(HWPF_5120_SDRAM0_BASE)
	li		t1, SDRAM_BANK0_MODE
	sll		t1, t1, SDRAM_BANK0_MODE_SHIFT
	add		t0, t1, t0
	lw		t1, 0(t0)

#if HWPF_5120_SDRAM_BANK_NUM == 2
	/* Program the mode register of SDRAM bank1 */
	li		t0, PA2VA(HWPF_5120_SDRAM1_BASE)
	li		t1, SDRAM_BANK1_MODE
	sll		t1, t1, SDRAM_BANK1_MODE_SHIFT
	add		t0, t1, t0
	lw		t1, 0(t0)
#endif	// ! HWPF_5120_SDRAM_BANK_NUM == 2

	/* SDRAM is ready now, put it to normal operation mode */
	or		t0, s0, DM_SDRAM_NORMAL_OP

	/* Clear DM_CLKEN_ALWAYS bit */
	li		t1, ~DM_CLKEN_ALWAYS
	and		t0, t0, t1
	sw		t0, MPMC_DM_CONTROL_REG(a1)

	/* Enable the Read/Write buffers of SDRAM bank0 */
	lw 		t0, MPMC_DM_CONFIG0_REG(a1)
	li		t1, DM_CFG_BUFFER_EN
	or		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG0_REG(a1)

#if HWPF_5120_SDRAM_BANK_NUM == 2
	/* Enable the Read/Write buffers of SDRAM bank1 */
	lw 		t0, MPMC_DM_CONFIG1_REG(a1)
	or		t0, t0, t1
	sw		t0, MPMC_DM_CONFIG1_REG(a1)
#endif  // ! HWPF_5120_SDRAM_BANK_NUM == 2

	jr		ra
	nop
END(init_mpmc_sdram)


.org 0x6D8

LEAF(_modinit)
	/********** SEE IF NOR FLASH ERASE WORKS WITHOUT ALL THIS SHIT **********/
	la		t0, 2f
	jr		t0
	nop

	/*=== Get back to Kseg1 to mimic the hard reset environment ===*/
	la		t0, 1f
	and		t0, ~MEM_SEG_MASK
	or		t0, MEM_KSEG1_BASE
	jr		t0
	nop

1:
	/* In Kseg1 unmapped and uncached */

	/* Turn on BEV bit */
	mfc0	t0, CP0_STATUS_REG
	or		t0, CP0_STATUS_BEV_BIT
	mtc0	t0, CP0_STATUS_REG

	/* Set IV bit */
	li		t0, CP0_CAUSE_IV_BIT
	mtc0	t0, CP0_CAUSE_REG

	/* Clear watch registers */
	mtc0	zero, CP0_WATCHLO_REG
	mtc0	zero, CP0_WATCHHI_REG

	/* Set Config0 register */
	li		t0, CP0_CONFIG0_DEFAULT
	mtc0	t0, CP0_CONFIG0_REG

	/* Re-initialize static RAM (FLASH) */
	bal		init_mpmc_sram
	nop

	/* Re-initialize cache */
	bal		init_cache
	nop

	/*=== Jump back to Kseg0 with cache enabled ===*/
	la		t0, 2f
	jr		t0
	nop

2:
	/*=== Back in Kseg0 unmapped but cached ===*/

	/****************************************************/
	/* It's necessary now to make a huge leap in faith. */
	/* We cannot test the initialization of SDRAM here  */
	/* because we are running in SDRAM right now!       */
	/* As part of the "real" bootloader we would be     */
	/* running out of FLASH ROM instead.                */
	/* Comparison of the disassembled code of the       */
	/* 'init_mpmc_sdram' function vs. the Hawking       */
	/* bootloader code shows good agreement.            */
	/****************************************************/

#if TEST_BOOTLOADER == 0
	/* Re-initialize SDRAM */
	bal		init_mpmc_sdram
	nop
#endif

	/* Get the next place we want to go, defined */
	/* as the start of this module plus 4K bytes */
	la		a0, init_cache
	addu	a0, a0, 4096

	/* Here we go... */
	jalr	a0
	nop

	/* Returning control to the real bootloader */
	/* Will never happen                        */
	jr		ra
	nop
END(_modinit)

.set reorder