xperiment.c

Boot code for ADM5120 with serial console for Edimax router.

/*****************************************************************************
;
;    Project : ADM5120
;    Creator : Dan Everett
;    File    : xperiment.c
;    Abstract: 
;
;*****************************************************************************/

#include <ctype.h>
#include <adm5120.h>
#include <mips4kc.h>
#include <flash.h>

#include <test_def.h>

void buart_print(char *str);
void ultoa(UINT n, char *str);
void btoa(char, char *);

void mx29lv320_enter_ss();
void mx29lv320_exit_ss();

#if TEST_BOOTLOADER == 1
extern int extiobyte_on;
extern unsigned short mx_mfg_id;
extern unsigned short mx_dev_id;
extern unsigned short mx_factory_protect;
extern unsigned long mx_ssv_lo;
extern unsigned long mx_ssv_med;
extern unsigned long mx_ssv_hi;
extern FLASH_DESC mx29lv320_dev;

void addr_test(unsigned int *p);
#endif


/**********************************************************/
/* reboot_router                                          */
/*		Causes the router to reboot                       */
/*		Tested and verified to work by DE                 */
/*		Soft resets are always vectored to BFC00000       */
/**********************************************************/

void reboot_router()
{
	/* Soft reset */
	ADM5120_SW_REG(SftRest_REG) = 1;
}


#if TEST_BOOTLOADER == 1

/****************/
/* hexdump		*/
/****************/

void hexdump(unsigned char *src, int size)
{
	volatile unsigned char *p = src;
	volatile unsigned char *preset = (unsigned char *) 0xbfc13c00;
	char c, buf[64];
	int i;

	*preset = 0xf0;

	for (i = 0; i < size; i++) {
		if (i % 8 == 0) {
			if (i % 16 == 0) {
				buart_print("\r\n");
				ultoa(i, buf);
				buart_print(buf);
				buart_print("   ");
			} else
				buart_print("-");
		} else
			buart_print(" ");

		c = *p++;
		btoa(c, buf);
		buart_print(buf);
	}

	buart_print("\r\n");
}


/****************/
/* hex2uint		*/
/****************/

unsigned int hex2uint(char *buf)
{
	unsigned int result = 0;
	int i, s;
	char c;

	for (i = 0; i < 8; i++) {
		c = buf[i];

		if (c >= '0' && c <= '9')
			c = c - '0';
		else if (c >= 'a' && c <= 'f')
			c = c - 'a' + 0x0A;
		else if (c >= 'A' && c <= 'F')
			c = c - 'a' + 0x0A;
		else
			continue;

		result += c << (28 - (4 * i));
	}

	return result;
}


/****************/
/* mem_peek		*/
/****************/

void mem_peek()
{
	volatile unsigned long *pData;
	unsigned long Data;
	char addrbuf[16];
	unsigned int d;

	buart_print("\r\nAddr: ");
	ReadLine(addrbuf, 8);
	d = hex2uint(addrbuf);
	pData = (unsigned long *) d;
	Data = *pData;
	buart_pair(Data, "Data");
}


/****************/
/* dump_ss		*/
/****************/

void dump_ss()
{
	mx29lv320_enter_ss();
	hexdump((unsigned char *) 0xbfc00000, 128);
//	hexdump((unsigned char *) 0xbfc00000, 65536);
	mx29lv320_exit_ss();
}


/****************/
/* toggle_extio	*/
/****************/

void toggle_extio()
{
	/* Hawking bootloader saves a byte of 0xFF to   */
	/* the ADM5120 register ext_IO_1 address.  What */
	/* does it do?                                  */
	volatile unsigned char *pio = (unsigned char *) 0xB0E00000;
	
	if (extiobyte_on) {
		buart_print("\r\next_IO_1 bye FF, setting to 00");
		*pio = 0x00;
		extiobyte_on = 0;
	} else {
		buart_print("\r\next_IO_1 bye 00, setting to FF");
		*pio = 0xFF;
		extiobyte_on = 1;
	}
}


/****************/
/* write_region	*/
/****************/

void write_region(unsigned char *region)
{
	unsigned char *flash = region;
	unsigned char *pRegionSave = 0;
	int i, rc, region_size = 8192;
	unsigned int ndelta = 0;
	unsigned int nff = 0;
	char buf[80];

	/* Read a FLASH sector.
	   Change one 32-bit word in it.
	   Erase the FLASH sector.
	   Write the changed data back to the sector. */

	pRegionSave = (unsigned char *) calloc(region_size, 1);

	if (pRegionSave != 0) {
		for (i = 0; i < region_size; i++)
			pRegionSave[i] = flash[i];

		buart_print("\r\nSA7 copied to RAM...");

		rc = flash_erase(flash, region_size);

		if (rc == FLASH_OK) {
			buart_print("\r\nSA7 erased");

			for (i = 0; i < region_size; i++) {
				if (flash[i] == 0xFF)
					nff++;
				if (pRegionSave[i] != flash[i])
					ndelta++;
			}

			ultoa(nff, buf);
			buart_print("\r\nNum 0xFF: ");
			buart_print(buf);

			ultoa(ndelta, buf);
			buart_print("\r\nNumber of changed bytes: ");
			buart_print(buf);
			buart_print("\r\n");

			strcpy((char *)(pRegionSave + 16), "You lousy cocksuckers!");

			rc = flash_write(flash, pRegionSave, region_size);

			if (rc == FLASH_OK) {
				buart_print("\r\nSA7 re-written\n\r");

				for (i = 0, nff = 0, ndelta = 0; i < region_size; i++) {
					if (flash[i] == 0xFF)
						nff++;
					if (pRegionSave[i] != flash[i])
						ndelta++;
				}
			} else
				buart_print("\r\nFLASH_ERROR from flash_write()");
		} else
			buart_print("\r\nFLASH_ERROR from flash_erase()");
	} else
		buart_print("\r\nERROR from calloc()");
}


/****************/
/* misc_info	*/
/****************/

#define NADDRTEST	10

void misc_info(UINT old_sp, UINT old_gp)
{
	UINT addrtest[NADDRTEST];
	UINT led_id, led_bit;
	UINT gpio_val;
	UINT mx_val;
	char buf[80];
	volatile unsigned char *ptemp;
	int i;

	for (i = 0; i < 80; i++) {
		buf[i] = 0;

		if (i < NADDRTEST)
			addrtest[i] = 0;
	}

	/* Show original $sp and $gp from the first */
	/* bootloader                               */

	ultoa(old_sp, buf);
	buart_print("\r\nOld $sp              : ");
	buart_print(buf);

	ultoa(old_gp, buf);
	buart_print(",   Old $gp              : ");
	buart_print(buf);

	/* Get some address numbers to check out */
	addr_test(&addrtest[0]);

	ultoa(addrtest[0], buf);
	buart_print("\r\nFirst address        : ");
	buart_print(buf);

	ultoa(addrtest[1], buf);
	buart_print(",   Second address       : ");
	buart_print(buf);
#if 1
	ultoa(addrtest[2], buf);
	buart_print("\r\nCP0 Status Register  : ");
	buart_print(buf);

	ultoa(addrtest[3], buf);
	buart_print(",   CP0 Config Register 0: ");
	buart_print(buf);

	ultoa(addrtest[4], buf);
	buart_print("\r\nCP0 Config Register 1: ");
	buart_print(buf);
#endif
	ultoa(addrtest[5], buf);
	buart_print(",   GP Register          : ");
	buart_print(buf);

	ultoa(addrtest[6], buf);
	buart_print("\r\nHeap at              : ");
	buart_print(buf);

	addrtest[7] = ADM5120_SW_REG(Mem_control_REG);
	ultoa(addrtest[7], buf);
	buart_print(",   SW REG MemControl Reg: ");
	buart_print(buf);

	addrtest[8] = ADM5120_SW_REG(VLAN_G1_REG);
	ultoa(addrtest[8], buf);
	buart_print("\r\nVLAN G1 Register     : ");
	buart_print(buf);

	ultoa(addrtest[9], buf);
	buart_print(",   PRId Register        : ");
	buart_print(buf);

	/* Flash security information */

	mx_mfg_id = 0x1234;
	mx_dev_id = 0x1234;
	mx_factory_protect = 0x1234;
	mx_ssv_hi = 0x0000;
	mx_ssv_med = 0x0000;
	mx_ssv_lo = 0x0000;

	mx_val = (UINT) mx29lv320_dev.start;
	ultoa(mx_val, buf);
	buart_print("\r\nFlash device start addr : ");
	buart_print(buf);

	/* Invoke the routine to collect the information */
	flash_info();

	mx_val = (UINT) mx_mfg_id;
	ultoa(mx_val, buf);
	buart_print("\r\nFlash manufacturer ID   : ");
	buart_print(buf);

	mx_val = (UINT) mx_dev_id;
	ultoa(mx_val, buf);
	buart_print("\r\nFlash device ID         : ");
	buart_print(buf);

	mx_val = (UINT) mx_factory_protect;
	ultoa(mx_val, buf);
	buart_print("\r\nFlash factory protect   : ");
	buart_print(buf);

	mx_val = (UINT) mx_ssv_hi;
	ultoa(mx_val, buf);
	buart_print("\r\nFlash protect hi        : ");
	buart_print(buf);

	mx_val = (UINT) mx_ssv_med;
	ultoa(mx_val, buf);
	buart_print("\r\nFlash protect med       : ");
	buart_print(buf);

	mx_val = (UINT) mx_ssv_lo;
	ultoa(mx_val, buf);
	buart_print("\r\nFlash protect lo        : ");
	buart_print(buf);

	buart_print("\r\n");

#if USE_LED_TEST == 1
	/* Just for kicks try out an LED */
	led_id = 4;
	led_bit = 1 << led_id;

	/* GPIO_conf0 register at offset B8 */
	gpio_val = *((UINT *) 0xB20000B8);

	/* Set GPIO line for output */
	gpio_val &= ~led_bit;

	/* Enable output */
	gpio_val |= (led_bit << 16);

	/* Output value ON */
	gpio_val |= (led_bit << 24);

	*((UINT *) 0xB20000B8) = gpio_val;
#endif
}
#endif


//	Getting an address via 'bal _get_pc' returns and address
//	in KSEG0 such as 80008E98
//
//	Getting an address via 'la somelabel' returns an address
//	in KSEG0 such as 80008EAC
//
//	======================================================================
//
//	CP0 Status register returns 00000C01
//
//		BEV (bit 22) is 0 meaining the exception vectors are "normal"
//
//		Hardware Interrupt Mask bits are set as follows:	0 0 0 0 1 1
//		Software Interrupt Mask bits are set as follows:	0 0
//
//		The base operating mode of the processor is Kernel
//		ERL = 0
//		EXL = 0
//
//		Interrupts are enabled since IE (bit 0) is 1
//
//	======================================================================
//
//	Config Register 0 is 80200083
//
//		M		(bit 31) is 1
//				means Config1 register is available with Select field = 1
//
//		???		bit 21 is set and this is among those reserved for
//				implementation options
//
//		BE		(bit 15) is 0
//				meaning the processor is in Little-Endian mode
//
//		AT		is 0
//				meaning the architecture type is MIPS32
//
//		AR		is 0
//				meaning the architecture revision level is Release 1
//
//		MT		is 1
//				meaning the MMU is a standard TLB
//
//		VI		is 0
//				meaning the instruction cache is not virtual
//
//		K0		is 3
//				meaning the Kseg0 coherency algortithm is "Cacheable"
//
//	======================================================================
//
//	Config Register 1 is 1E994C8A
//				0 001111 010 011 001 010 011 001 0 0 0 1 0 1 0
//
//		M		(bit 31) is 0
//				meaning Config2 and Config3 registers are not present
//
//		MMU Size-1 is 15
//				meaning there are 16 TLB entries
//
//		IS		is 2
//				meaning there are 256 ICACHE sets per way
//
//		IL		is 3
//				meaning the ICACHE line size is 16 bytes
//
//		IA		is 1
//				meaning the ICACHE associativity is 2-way
//
//		DS		is 2
//				meaning there are 256 DCACHE sets per way
//
//		DL		is 3
//				meaning the DCACHE line size is 16 bytes
//
//		DA		is 1
//				meaning the DCACHE associativity is 2-way
//
//		C2		(bit 6) is 0
//				meaning there is no Coprocessor 2
//
//		PC		(bit 4) is 0
//				meaning there are no performance counter registers
//
//		WR		(bit 3) is 1
//				meaning the Watch registers are available
//
//		EP		(bit 1) is 1
//				meaning that EJTAG is implemented
//
//		FP		(bit 0) is 0
//				meaning there is no FPU
//
//
//	======================================================================
//
//	PRId Register is 0001800B
//				00000000 00000001 10000000 00001011
//
//		R		(bits 24 through 31) is 0
//				reserved and must be read as 0
//
//		CId		(bits 16 through 23) is 1
//				meaning that MIPS Technologies designed the core
//
//		PRId	(bits 8 through 15) is 0x80
//				meaning this is a 4Kc core
//
//		Rev		(bits 0 through 7) is 3
//				meaning the revision number of the processor is
//				either 2.5 or 2.6
//
//	======================================================================
//
//	SW Mem_control_REG is 00050400
//				0000000000000 101 00000 100 00 0 00 000
//
//		SRAM1_Size is 101
//				meaning 8 MBytes (NOTE: There is no SRAM1 on the board!)
//
//		SRAM0_Size is 100
//				meaning 4 MBytes (NOTE: This is correct!)
//
//		SDRAM1_en (bit 5) is 0
//				meaning there is no second SDRAM chip (This is wrong!)
//
//		SDRAMsize (bits 0 through 2) is 0
//				meaning the size of the first SDRAM chip is "reserved"
//				(This is wrong!)
//
//	======================================================================
//
//	VLAN G1 Register is 0000007F
//