nor_ldrinit.s

Boot code for ADM5120 with serial console for Edimax router.

/*****************************************************************************
;
;    Project : ADM5120
;    Creator : Dan Everett
;    File    : ldrinit.S
;    Abstract: 
;
;*****************************************************************************/

#include <mips.h>
#include <mips4kc.h>
#include <asm.h>
#include <adm5120.h>

#include <test_def.h>

#define SYS_STACK_SIZE		0x4000

.text

.set noreorder

LEAF(_ldrinit)

//#if TEST_BOOTLOADER == 1
	/* Go directly to c_start for testing */
	la		a0, safe_start2
	jr		a0
	nop
//#endif

	/* Get current position */
	bal		_get_pc
	nop

	/* v0 now holds the run time address of _mark1 */

_mark1:
	move	a0, v0
	la		a1, _ldrinit
	la		t0, _mark1
	
	/* Calculate the offset from _ldrinit to _mark1 */
	subu	t0, t0, a1		// t0 holds the length from _ldrinit to _mark1
	subu	a0, a0, t0		// a0 holds the start address of _ldrinit in ROM
	move	s0, a0

	la		t1, _etext
	subu	a2, t1, a1		// a2 holds the length of the program
	
	/*
	 *  Copy the program code from ROM to SDRAM
	 *		a0 : Source address of program image in ROM
	 *		a1 : Destination address
	 *		a2 : length of program image
	 */
	 
	 /*  Copy code loop  */
1:
	lw		t0, 0(a0)
	subu	a2, a2, 4*4			// subtract the length to be copied
	lw		t1, 4(a0)
	sw		t0, 0(a1)
	lw		t2, 8(a0)	
	sw		t1, 4(a1)
	lw		t3, 12(a0)
	sw		t2, 8(a1)
	addu	a0, a0, 4*4			// next source address
	sw		t3, 12(a1)

	/*
	 *  Invalidate the corresponding ICACHE line
	 */
 
	cache	ICACHE_HIT_INVALIDATE, 0(a1)
	bgtz	a2, 1b
	addu	a1, a1, 4*4				// next destination address (note branch delay slot)

	la		a0, _ldrinit
	la		a1, _etext				// start of data segment 

	subu	a0, a1, a0
	addu	a0, s0, a0				// start of data in ROM

	la		a2, _edata				// end of data segment
	subu	a2, a2, a1				// length of data segment

	/*
	 *  Copy the program data from ROM to SDRAM
	 *		a0 : Source address of program image in ROM
	 *		a1 : Destination address
	 *		a2 : length of program image
	 */

	 /*  Copy data loop  */
1:
	lw		t0, 0(a0)
	subu	a2, a2, 4*4			// subtract the length to be copied
	lw		t1, 4(a0)
	sw		t0, 0(a1)
	lw		t2, 8(a0)	
	sw		t1, 4(a1)
	lw		t3, 12(a0)
	sw		t2, 8(a1)
	addu	a0, a0, 4*4			// next source address
	sw		t3, 12(a1)

	bgtz	a2, 1b
	addu	a1, a1, 4*4			// next destination address (note branch delay slot)

	/* Jump to code now in SDRAM */
	la		t0, 2f				
	jr		t0
	nop
2:			
	/* We are in SDRAM now */

safe_start2:

	/* Clear BSS section */
	la		a0, __bss_start
	la		a1, _end
	subu	a1, a1, a0

	/* Clear BSS Loop */
3:
	sw		zero, 0(a0)
	sw		zero, 4(a0)
	subu	a1, a1, 4*4			// subtract the length to be zeroed
	sw		zero, 8(a0)
	sw		zero, 12(a0)
	bgtz	a1, 3b
	addu	a0, a0, 4*4			// next destination address (note branch delay slot)

	/* Save whatever was in $sp and $gp and */
	/* pass them as arguments to c_start    */
	move	a0, sp
	move	a1, gp

	/* Load gp */
	la		gp, _gp
	
	/* Initialize stack */
	la		t0, _end
	li		t1, SYS_STACK_SIZE
	add		sp, t0, t1
	
	/* Align sp to 16-byte boundary */
	li		t0, ~0xf
	and		sp, sp, t0

	/* Store the first free memory address */
	addu	t0, sp, 0x10
	la		t1, _heap_h
	sw		t0, 0(t1)

	/* Call c_entry and never return */
	jal		c_entry
	nop

	/* Never Reached */

	/* MOD BOOT - IN CASE WE EVER GET BACK HERE GO BACK TO REAL BOOTLOADER */
	jr		ra
	nop

1:	
	b		1b
	nop
END(_ldrinit)


/* Get program counter */
LEAF(_get_pc)
	jr		ra
	move	v0, ra				// note branch delay slot
END(_get_pc)


LEAF(_icache_sync_all)
	mtc0	zero, CP0_TAGLO_REG
	mtc0	zero, CP0_TAGHI_REG
	li		a0, MEM_KSEG0_BASE
	addiu	a1, a0, CPU_ICACHE_DFE_SIZE - 0x10*8

1:
	cache	ICACHE_INDEX_STORETAG, 0x00(a0)
	cache	ICACHE_INDEX_STORETAG, 0x10(a0)
	cache	ICACHE_INDEX_STORETAG, 0x20(a0)
	cache	ICACHE_INDEX_STORETAG, 0x30(a0)
	cache	ICACHE_INDEX_STORETAG, 0x40(a0)
	cache	ICACHE_INDEX_STORETAG, 0x50(a0)
	cache	ICACHE_INDEX_STORETAG, 0x60(a0)
	cache	ICACHE_INDEX_STORETAG, 0x70(a0)
	bne		a0, a1, 1b
	addiu	a0, a0, 0x10*8		// note branch delay slot

	jr		ra
	nop							// note branch delay slot
END(_icache_sync_all)

.set reorder