memdev.h

Boot code for ADM5120 with serial console for Edimax router.

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;------------------------------------------------------------------------------
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;    Project : ADM5120
;    Creator : 
;    File    : memdev.h
;    Abstract: 
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;Modification History:
; 
;
;*****************************************************************************/

#ifndef __MEMDEV_H__
#define __MEMDEV_H__

#define ENABLE                                  1
#define DISABLE                                 0

// SDRAM0 Specs

// IMPORTANT UPDATE: 17 MAY 2006
// It has been learned that there is actually only ONE "bank" of SDRAM
// in the H2WR54G.  There are 2 SDRAM chips, but they share all
// address lines, bank-select lines and chip-select lines.  One has
// its 16 data output lines connected to the low side of the 32-bit
// data bus and the other is connected to the high side.

// Bus width of SDRAM bank0. legal values are 16 or 32
// #define BOARD_SDRAM0_BUS_WIDTH				16
#define BOARD_SDRAM0_BUS_WIDTH					32
// DE - I had this as 16 but the actual router
// flash shows it should be 32

// memory size of SDRAM chip in Mbits
#define BOARD_SDRAM0_DEV_SIZE					128
// DE - I thought about making this 25 in light of the 5-17-2006 note above.
// But the MPMC doesn't know there are really 2 chips out there
// responding to it, right?  Still, there will be 32 data lines that
// the MPMC will need to be aware of.  Furthermore, each chip knows
// it's only a 128 Mb part so the row and column lengths must
// be appropriate for it, and changing this to 256 would change
// those values.  FWIW this is still just as confusing as it was
// when I first looked at it 18 months ago.

// data bus width of SDRAM chip. legal value are 8, 16 or 32
#define BOARD_SDRAM0_DEV_DATA_WIDTH				16


// SDRAM1 Specs

// Enable to do it "right"
// NOTE: DE 5-17-2006 see note above.  Since both
// chips share address and control lines, this
// should not be enabled.
// Disable to match what's on the H2WR54G router as shipped
//#define BOARD_5120_SDRAM1_STATUS				ENABLE
#define BOARD_5120_SDRAM1_STATUS				DISABLE
// DE - Changed to DISABLE (5-17-2006)

// Bus width of SDRAM bank1. legal values are 16 or 32
// #define BOARD_SDRAM1_BUS_WIDTH				16
#define BOARD_SDRAM1_BUS_WIDTH					32
// DE - I had this as 16 but the actual router
// flash shows it should be 32

// memory size of SDRAM chip in Mbits
#define BOARD_SDRAM1_DEV_SIZE				    128

// data bus width of SDRAM chip. legal value are 8, 16 or 32
#define BOARD_SDRAM1_DEV_DATA_WIDTH			    16

#endif