adm5120.h

Boot code for ADM5120 with serial console for Edimax router.

/* Send_trig_REG */
#define SEND_TRIG_LOW							0x0001
#define SEND_TRIG_HIGH							0x0002


/* Srch_cmd_REG */
#define SW_MAC_SEARCH_START						0x000001
#define SW_MAX_SEARCH_AGAIN						0x000002


/* MAC_wt0_REG */
#define SW_MAC_WRITE							0x00000001
#define SW_MAC_WRITE_DONE						0x00000002
#define SW_MAC_FILTER_EN						0x00000004
#define SW_MAC_VLANID_SHIFT						3
#define SW_MAC_VLANID_MASK						0x00000038
#define SW_MAC_VLANID_EN						0x00000040
#define SW_MAC_PORTMAP_MASK						0x00001F80
#define SW_MAC_PORTMAP_SHIFT					7
#define SW_MAC_AGE_MASK							(0x7 << 13)
#define SW_MAC_AGE_STATIC						(0x7 << 13)
#define SW_MAC_AGE_VALID						(0x1 << 13)
#define SW_MAC_AGE_EMPTY						0

/* BW_cntl0_REG */
#define SW_PORT_TX_NOLIMIT						0
#define SW_PORT_TX_64K							1
#define SW_PORT_TX_128K							2
#define SW_PORT_TX_256K							3
#define SW_PORT_TX_512K							4
#define SW_PORT_TX_1M							5
#define SW_PORT_TX_4M							6
#define SW_PORT_TX_10MK							7

/* BW_cntl1_REG */
#define SW_TRAFFIC_SHAPE_IPG					(0x1 << 31)

/* PHY_cntl0_REG */
#define SW_PHY_ADDR_MASK						0x0000001F
#define PHY_ADDR_MAX							0x1f
#define SW_PHY_REG_ADDR_MASK					0x00001F00
#define SW_PHY_REG_ADDR_SHIFT					8
#define PHY_REG_ADDR_MAX						0x1f
#define SW_PHY_WRITE							0x00002000
#define SW_PHY_READ								0x00004000
#define SW_PHY_WDATA_MASK						0xFFFF0000
#define SW_PHY_WDATA_SHIFT						16


/* PHY_cntl1_REG */
#define SW_PHY_WRITE_DONE						0x00000001
#define SW_PHY_READ_DONE						0x00000002
#define SW_PHY_RDATA_MASK						0xFFFF0000
#define SW_PHY_RDATA_SHIFT						16

/* FC_th_REG */
/* Adj_port_th_REG */
/* Port_th_REG */

/* PHY_cntl2_REG */
#define SW_PHY_AN_MASK							0x0000001F
#define SW_PHY_SPD_MASK							0x000003E0
#define SW_PHY_SPD_SHIFT						5
#define SW_PHY_DPX_MASK							0x00007C00
#define SW_PHY_DPX_SHIFT						10
#define SW_FORCE_FC_MASK						0x000F8000
#define SW_FORCE_FC_SHIFT						15
#define SW_PHY_NORMAL_MASK						0x01F00000
#define SW_PHY_NORMAL_SHIFT						20
#define SW_PHY_AUTOMDIX_MASK					0x3E000000
#define SW_PHY_AUTOMDIX_SHIFT					25
#define SW_PHY_REC_MCCAVERAGE					0x40000000


/* PHY_cntl3_REG */
/* Pri_cntl_REG */
/* VLAN_pri_REG */
/* TOS_en_REG */
/* TOS_map0_REG */
/* TOS_map1_REG */
/* Custom_pri1_REG */
/* Custom_pri2_REG */
/* Empty_cnt_REG */
/* Port_cnt_sel_REG */
/* Port_cnt_REG */

/* PHY_cntl4_REG */
#define PHY_VOLT23								(0x1 << 20)
#define PHY_ROMCODE_25							(0x1 << 21)

/* SW_Int_st_REG & SW_Int_mask_REG */
#define SEND_H_DONE_INT							0x0000001
#define SEND_L_DONE_INT							0x0000002
#define RX_H_DONE_INT							0x0000004
#define RX_L_DONE_INT							0x0000008
#define RX_H_DESC_FULL_INT						0x0000010
#define RX_L_DESC_FULL_INT						0x0000020
#define PORT0_QUE_FULL_INT						0x0000040
#define PORT1_QUE_FULL_INT						0x0000080
#define PORT2_QUE_FULL_INT						0x0000100
#define PORT3_QUE_FULL_INT						0x0000200
#define PORT4_QUE_FULL_INT						0x0000400
#define PORT5_QUE_FULL_INT						0x0000800

#define CPU_QUE_FULL_INT						0x0002000
#define GLOBAL_QUE_FULL_INT						0x0004000
#define MUST_DROP_INT							0x0008000
#define BC_STORM_INT							0x0010000

#define PORT_STATUS_CHANGE_INT					0x0040000
#define INTRUDER_INT							0x0080000
#define	WATCHDOG0_EXPR_INT						0x0100000
#define WATCHDOG1_EXPR_INT						0x0200000
#define RX_DESC_ERR_INT							0x0400000
#define SEND_DESC_ERR_INT						0x0800000
#define CPU_HOLD_INT							0x1000000
#define SWITCH_INT_MASK							0x1FDEFFF


/* GPIO_conf0_REG */
#define GPIO0_INPUT_MODE						0x00000001
#define GPIO1_INPUT_MODE						0x00000002
#define GPIO2_INPUT_MODE						0x00000004
#define GPIO3_INPUT_MODE						0x00000008
#define GPIO4_INPUT_MODE						0x00000010
#define GPIO5_INPUT_MODE						0x00000020
#define GPIO6_INPUT_MODE						0x00000040
#define GPIO7_INPUT_MODE						0x00000080

#define GPIO0_OUTPUT_MODE						0
#define GPIO1_OUTPUT_MODE						0
#define GPIO2_OUTPUT_MODE						0
#define GPIO3_OUTPUT_MODE						0
#define GPIO4_OUTPUT_MODE						0
#define GPIO5_OUTPUT_MODE						0
#define GPIO6_OUTPUT_MODE						0
#define GPIO7_OUTPUT_MODE						0

#define GPIO0_INPUT_MASK						0x00000100
#define GPIO1_INPUT_MASK						0x00000200
#define GPIO2_INPUT_MASK						0x00000400
#define GPIO3_INPUT_MASK						0x00000800
#define GPIO4_INPUT_MASK						0x00001000
#define GPIO5_INPUT_MASK						0x00002000
#define GPIO6_INPUT_MASK						0x00004000
#define GPIO7_INPUT_MASK						0x00008000

#define GPIO0_OUTPUT_EN							0x00010000
#define GPIO1_OUTPUT_EN							0x00020000
#define GPIO2_OUTPUT_EN							0x00040000
#define GPIO3_OUTPUT_EN							0x00080000
#define GPIO4_OUTPUT_EN							0x00100000
#define GPIO5_OUTPUT_EN							0x00200000
#define GPIO6_OUTPUT_EN							0x00400000
#define GPIO7_OUTPUT_EN							0x00800000

#define GPIO_CONF0_OUTEN_MASK					0x00ff0000

#define GPIO0_OUTPUT_HI							0x01000000
#define GPIO1_OUTPUT_HI							0x02000000
#define GPIO2_OUTPUT_HI							0x04000000
#define GPIO3_OUTPUT_HI							0x08000000
#define GPIO4_OUTPUT_HI							0x10000000
#define GPIO5_OUTPUT_HI							0x20000000
#define GPIO6_OUTPUT_HI							0x40000000
#define GPIO7_OUTPUT_HI							0x80000000

#define GPIO0_OUTPUT_LOW						0
#define GPIO1_OUTPUT_LOW						0
#define GPIO2_OUTPUT_LOW						0
#define GPIO3_OUTPUT_LOW						0
#define GPIO4_OUTPUT_LOW						0
#define GPIO5_OUTPUT_LOW						0
#define GPIO6_OUTPUT_LOW						0
#define GPIO7_OUTPUT_LOW						0


/* GPIO_conf2_REG */
#define EXTIO_WAIT_EN							(0x1 << 6)
#define EXTIO_CS1_INT1_EN						(0x1 << 5)
#define EXTIO_CS0_INT0_EN						(0x1 << 4)

/* Watchdog0_REG, Watchdog1_REG */
#define WATCHDOG0_RESET_EN						0x80000000
#define WATCHDOG1_DROP_EN						0x80000000

#define WATCHDOG_TIMER_SET_MASK					0x7FFF0000
#define WATCHDOG_TIMER_SET_SHIFT				16
#define WATCHDOG_TIMER_MASK						0x00007FFF


/* Timer_int_REG */
#define SW_TIMER_INT_DISABLE					0x10000
#define SW_TIMER_INT							0x1

/* Timer_REG */
#define SW_TIMER_EN								0x10000
#define SW_TIMER_MASK							0xffff
#define SW_TIMER_10MS_TICKS						0x3D09
#define SW_TIMER_1MS_TICKS						0x61A
#define SW_TIMER_100US_TICKS					0x9D


/* Port0_LED_REG, Port1_LED_REG, Port2_LED_REG, Port3_LED_REG, Port4_LED_REG*/
#define GPIOL_INPUT_MODE						0x00
#define GPIOL_OUTPUT_FLASH						0x01
#define GPIOL_OUTPUT_LOW						0x02
#define GPIOL_OUTPUT_HIGH						0x03
#define GPIOL_LINK_LED							0x04
#define GPIOL_SPEED_LED							0x05
#define GPIOL_DUPLEX_LED						0x06
#define GPIOL_ACT_LED							0x07
#define GPIOL_COL_LED							0x08
#define GPIOL_LINK_ACT_LED						0x09
#define GPIOL_DUPLEX_COL_LED					0x0A
#define GPIOL_10MLINK_ACT_LED					0x0B
#define GPIOL_100MLINK_ACT_LED					0x0C
#define GPIOL_CTRL_MASK							0x0F

#define GPIOL_INPUT_MASK						0x7000
#define GPIOL_INPUT_0_MASK						0x1000
#define GPIOL_INPUT_1_MASK						0x2000
#define GPIOL_INPUT_2_MASK						0x4000

#define PORT_LED0_SHIFT							0
#define PORT_LED1_SHIFT							4
#define PORT_LED2_SHIFT							8


/*===========================  UART Control Register  ========================*/
#define UART_DR_REG								0x00
#define UART_RSR_REG							0x04
#define UART_ECR_REG							0x04
#define UART_LCR_H_REG							0x08
#define UART_LCR_M_REG							0x0c
#define UART_LCR_L_REG							0x10
#define UART_CR_REG								0x14
#define UART_FR_REG								0x18
#define UART_IIR_REG							0x1c
#define UART_ICR_REG							0x1C
#define UART_ILPR_REG							0x20

/*  rsr/ecr reg  */
#define UART_OVERRUN_ERR						0x08
#define UART_BREAK_ERR							0x04
#define UART_PARITY_ERR							0x02
#define UART_FRAMING_ERR						0x01
#define UART_RX_STATUS_MASK						0x0f
#define UART_RX_ERROR							( UART_BREAK_ERR	\
												| UART_PARITY_ERR	\
												| UART_FRAMING_ERR)

/*  lcr_h reg  */
#define UART_SEND_BREAK							0x01
#define UART_PARITY_EN							0x02
#define UART_EVEN_PARITY						0x04
#define UART_TWO_STOP_BITS						0x08
#define UART_ENABLE_FIFO						0x10

#define UART_WLEN_5BITS							0x00
#define UART_WLEN_6BITS							0x20
#define UART_WLEN_7BITS							0x40
#define UART_WLEN_8BITS							0x60
#define UART_WLEN_MASK							0x60

/*  cr reg  */
#define UART_PORT_EN							0x01
#define UART_SIREN								0x02
#define UART_SIRLP								0x04
#define UART_MODEM_STATUS_INT_EN				0x08
#define UART_RX_INT_EN							0x10
#define UART_TX_INT_EN							0x20
#define UART_RX_TIMEOUT_INT_EN					0x40
#define UART_LOOPBACK_EN						0x80

/*  fr reg  */
#define UART_CTS								0x01
#define UART_DSR								0x02
#define UART_DCD								0x04
#define UART_BUSY								0x08
#define UART_RX_FIFO_EMPTY						0x10
#define UART_TX_FIFO_FULL						0x20
#define UART_RX_FIFO_FULL						0x40
#define UART_TX_FIFO_EMPTY						0x80

/*  iir/icr reg  */
#define UART_MODEM_STATUS_INT					0x01
#define UART_RX_INT								0x02
#define UART_TX_INT								0x04
#define UART_RX_TIMEOUT_INT						0x08

#define UART_INT_MASK							0x0f

#define ADM5120_UARTCLK_FREQ					62500000

#define UART_BAUDDIV(_rate)				\
	((UINT32)(ADM5120_UARTCLK_FREQ/(16*(_rate)) - 1))

/*  uart_baudrate  */
#define UART_230400bps_DIVISOR					UART_BAUDDIV(230400)
// #define UART_115200bps_DIVISOR					UART_BAUDDIV(115200)
#define UART_115200bps_DIVISOR					33
// #define UART_76800bps_DIVISOR					UART_BAUDDIV(76800)
#define UART_76800bps_DIVISOR					50
// #define UART_57600bps_DIVISOR					UART_BAUDDIV(57600)
#define UART_57600bps_DIVISOR					67
//#define UART_38400bps_DIVISOR					UART_BAUDDIV(38400)
#define UART_38400bps_DIVISOR					102
//#define UART_19200bps_DIVISOR					UART_BAUDDIV(19200)
#define UART_19200bps_DIVISOR					202
//#define UART_14400bps_DIVISOR					UART_BAUDDIV(14400)
#define UART_14400bps_DIVISOR					270
//#define UART_9600bps_DIVISOR					UART_BAUDDIV(9600)
#define UART_9600bps_DIVISOR					406
//#define UART_2400bps_DIVISOR					UART_BAUDDIV(2400)
#define UART_2400bps_DIVISOR					1627
//#define UART_1200bps_DIVISOR					UART_BAUDDIV(1200)
#define UART_1200bps_DIVISOR					3254


/* Cache Controller */
//#define ADM5120_CACHE_CTRL_BASE				0x70000000
#define ADM5120_CACHE_LINE_SIZE				16
//#define ADM5120_CACHE_CTRL_REGSIZE				4

/* NAND flash interface */
#define NAND_RW_REG                             0x00
#define NAND_CLR_CE_REG                       0x01
#define NAND_SET_CE_REG                         0x02
#define NAND_CLR_CLE_REG                      0x03
#define NAND_SET_CLE_REG                        0x04
#define NAND_CLR_ALE_REG                      0x05
#define NAND_SET_ALE_REG                        0x06
#define NAND_SET_SPn_REG                       0x07
#define NAND_CLR_SPn_REG                         0x08
#define NAND_CLR_WP_REG                       0x09
#define NAND_SET_WP_REG                         0x0a
#define NAND_RDY_REG                            0x0b

#define NAND_SET_BIT                            0x01
#define NAND_ENABLE                             0x100

/* Macros for accessing NAND flash interface register */
#define ADM5120_NAND_REG(_reg)		\
	(*((volatile unsigned long *)(PA2VA(ADM5120_SMEM1_BASE + (_reg)))))

#endif