adm5120.h

Boot code for ADM5120 with serial console for Edimax router.

#define IRQ_MODE_REG							0x14	/* Read/Write */
#define FIQ_STATUS_REG							0x18	/* Read */

/* test registers */
#define IRQ_TESTSRC_REG							0x1c	/* Read/Write */
#define IRQ_SRCSEL_REG							0x20	/* Read/Write */
#define IRQ_LEVEL_REG							0x24	/* Read/Write */

/*  Macro for accessing Interrupt controller register  */
#define ADM5120_INTC_REG(_reg)		\
	(*((volatile unsigned long *)(PA2VA(ADM5120_INTC_BASE + (_reg)))))

/* interrupt levels */
#define INT_LVL_TIMER							0	/* Timer */
#define INT_LVL_UART0							1	/* Uart 0 */
#define INT_LVL_UART1							2	/* Uart 1 */
#define INT_LVL_USBHOST							3	/* USB Host */
#define INT_LVL_EXTIO_0							4	/* External I/O 0 */
#define INT_LVL_EXTIO_1							5	/* External I/O 1 */
#define INT_LVL_PCI_0							6	/* PCI 0 */
#define INT_LVL_PCI_1							7	/* PCI 1 */
#define INT_LVL_PCI_2							8	/* PCI 2 */
#define INT_LVL_SWITCH							9	/* Switch */
#define INT_LVL_MAX								INT_LVL_SWITCH	

/* interrupts */
#define IRQ_TIMER								(0x1 << INT_LVL_TIMER)
#define IRQ_UART0								(0x1 << INT_LVL_UART0)
#define IRQ_UART1								(0x1 << INT_LVL_UART1)
#define IRQ_USBHOST								(0x1 << INT_LVL_USBHOST)
#define IRQ_EXTIO_0								(0x1 << INT_LVL_EXTIO_0)
#define IRQ_EXTIO_1								(0x1 << INT_LVL_EXTIO_1)
#define IRQ_PCI_INT0							(0x1 << INT_LVL_PCI_0)
#define IRQ_PCI_INT1							(0x1 << INT_LVL_PCI_1)
#define IRQ_PCI_INT2							(0x1 << INT_LVL_PCI_2)
#define IRQ_SWITCH								(0x1 << INT_LVL_SWITCH)

#define IRQ_MASK								0x3ff


/* IRQ LEVEL reg */
#define IRQ_EXTIO0_ACT_LOW						IRQ_EXTIO_0
#define IRQ_EXTIO1_ACT_LOW						IRQ_EXTIO_1
#define IRQ_PCIINT0_ACT_LOW						IRQ_PCI_INT0
#define IRQ_PCIINT1_ACT_LOW						IRQ_PCI_INT1
#define IRQ_PCIINT2_ACT_LOW						IRQ_PCI_INT2

#define IRQ_LEVEL_MASK							0x01F0

/*=========================  Switch Control Register  ========================*/
/* Control Register */
#define CODE_REG								0x0000
#define SftRest_REG								0x0004
#define Boot_done_REG							0x0008
#define SWReset_REG								0x000C
#define Global_St_REG							0x0010
#define PHY_st_REG								0x0014
#define Port_st_REG								0x0018
#define Mem_control_REG							0x001C	
#define SW_conf_REG								0x0020
#define CPUp_conf_REG							0x0024
#define Port_conf0_REG							0x0028
#define Port_conf1_REG							0x002C
#define Port_conf2_REG							0x0030

#define VLAN_G1_REG								0x0040
#define VLAN_G2_REG								0x0044
#define Send_trig_REG							0x0048
#define Srch_cmd_REG							0x004C
#define ADDR_st0_REG							0x0050
#define ADDR_st1_REG							0x0054
#define MAC_wt0_REG								0x0058
#define MAC_wt1_REG								0x005C
#define BW_cntl0_REG							0x0060
#define BW_cntl1_REG							0x0064
#define PHY_cntl0_REG							0x0068
#define PHY_cntl1_REG							0x006C
#define FC_th_REG								0x0070
#define Adj_port_th_REG							0x0074
#define Port_th_REG								0x0078
#define PHY_cntl2_REG							0x007C
#define PHY_cntl3_REG							0x0080
#define Pri_cntl_REG							0x0084
#define VLAN_pri_REG							0x0088
#define TOS_en_REG								0x008C
#define TOS_map0_REG							0x0090
#define TOS_map1_REG							0x0094
#define Custom_pri1_REG							0x0098
#define Custom_pri2_REG							0x009C
#define PHY_cntl4_REG							0x00A0
#define Empty_cnt_REG							0x00A4
#define Port_cnt_sel_REG						0x00A8
#define Port_cnt_REG							0x00AC
#define SW_Int_st_REG							0x00B0
#define SW_Int_mask_REG							0x00B4

// GPIO config
#define GPIO_conf0_REG							0x00B8
#define GPIO_conf2_REG							0x00BC

// Watch dog
#define Watchdog0_REG							0x00C0
#define Watchdog1_REG							0x00C4

#define Swap_in_REG								0x00C8
#define Swap_out_REG							0x00CC

// Tx/Rx Descriptors
#define Send_HBaddr_REG							0x00D0
#define Send_LBaddr_REG							0x00D4
#define Recv_HBaddr_REG							0x00D8
#define Recv_LBaddr_REG							0x00DC
#define Send_HWaddr_REG							0x00E0
#define Send_LWaddr_REG							0x00E4
#define Recv_HWaddr_REG							0x00E8
#define Recv_LWaddr_REG							0x00EC

// Timer Control 
#define Timer_int_REG							0x00F0
#define Timer_REG								0x00F4

// LED control
#define Port0_LED_REG							0x0100
#define Port1_LED_REG							0x0104
#define Port2_LED_REG							0x0108
#define Port3_LED_REG							0x010c
#define Port4_LED_REG							0x0110


/* Macros for accessing Switch control register */
#define ADM5120_SW_REG(_reg)		\
	(*((volatile unsigned long *)(PA2VA(ADM5120_SWCTRL_BASE + (_reg)))))



/* CODE_REG */
#define CODE_ID_MASK							0x00FFFF
#define CODE_ADM5120_ID							0x5120

#define CODE_REV_MASK							0x0F0000
#define CODE_REV_SHIFT							16
#define CODE_REV_ADM5120_0						0x8

#define CODE_CLK_MASK							0x300000
#define CODE_CLK_SHIFT							20

#define CPU_CLK_175MHZ							0x0
#define CPU_CLK_200MHZ							0x1
#define CPU_CLK_225MHZ							0x2
#define CPU_CLK_250MHZ							0x3

#define CPU_NAND_BOOT							(0x1 << 24)
#define CPU_DCACHE_2K_WAY						(0x1 << 25)
#define CPU_DCACHE_2WAY							(0x1 << 26)
#define CPU_ICACHE_2K_WAY						(0x1 << 27)
#define CPU_ICACHE_2WAY							(0x1 << 28)
#define CPU_PQFP_TYPE							(0x1 << 29)


#define CPU_GMII_SUPPORT						0x20000000

#define CPU_CACHE_LINE_SIZE						16
#define CPU_ICACHE_DFE_SIZE						0x2000
#define CPU_DCACHE_DEF_SIZE						0x2000

/* SftRest_REG	*/
#define SOFTWARE_RESET							0x1

/* Boot_done_REG */
#define BOOT_DONE								0x1

/* SWReset_REG */
#define SWITCH_RESET							0x1

/* Global_St_REG */
#define DATA_BUF_BIST_FAILED					(0x1 << 0)
#define LINK_TAB_BIST_FAILED					(0x1 << 1)
#define MC_TAB_BIST_FAILED						(0x1 << 2)
#define ADDR_TAB_BIST_FAILED					(0x1 << 3)
#define DCACHE_D_FAILED							(0x3 << 4)
#define DCACHE_T_FAILED							(0x1 << 6)
#define ICACHE_D_FAILED							(0x3 << 7)
#define ICACHE_T_FAILED							(0x1 << 9)
#define BIST_FAILED_MASK						0x03FF

#define ALLMEM_TEST_DONE						(0x1 << 10)

#define SKIP_BLK_CNT_MASK						0x1FF000
#define SKIP_BLK_CNT_SHIFT						12


/* PHY_st_REG */
#define PORT_LINK_MASK							0x0000001F
#define PORT_MII_LINKFAIL						0x00000020
#define PORT_SPEED_MASK							0x00001F00

#define PORT_GMII_SPD_MASK						0x00006000
#define PORT_GMII_SPD_10M						0
#define PORT_GMII_SPD_100M						0x00002000
#define PORT_GMII_SPD_1000M						0x00004000

#define PORT_DUPLEX_MASK						0x003F0000
#define PORT_FLOWCTRL_MASK						0x1F000000

#define PORT_GMII_FLOWCTRL_MASK					0x60000000
#define PORT_GMII_FC_ON							0x20000000
#define PORT_GMII_RXFC_ON						0x20000000
#define PORT_GMII_TXFC_ON						0x40000000

/* Port_st_REG */
#define PORT_SECURE_ST_MASK						0x001F
#define MII_PORT_TXC_ERR						0x0080

/* Mem_control_REG */
#define SDRAM_SIZE_4MBYTES						0x0001
#define SDRAM_SIZE_8MBYTES						0x0002
#define SDRAM_SIZE_16MBYTES						0x0003
#define SDRAM_SIZE_64MBYTES						0x0004
#define SDRAM_SIZE_128MBYTES					0x0005
#define SDRAM_SIZE_MASK							0x0007

#define MEMCNTL_SDRAM1_EN						(0x1 << 5)

#define ROM_SIZE_DISABLE						0x0000
#define ROM_SIZE_512KBYTES						0x0001
#define ROM_SIZE_1MBYTES						0x0002
#define	ROM_SIZE_2MBYTES						0x0003
#define ROM_SIZE_4MBYTES						0x0004
#define ROM_SIZE_8MBYTES						0x0005
#define ROM_SIZE_MASK							0x0007

#define ROM0_SIZE_SHIFT							8
#define ROM1_SIZE_SHIFT							16


/* SW_conf_REG */
#define SW_AGE_TIMER_MASK						0x000000F0
#define SW_AGE_TIMER_DISABLE					0x0
#define SW_AGE_TIMER_FAST						0x00000080
#define SW_AGE_TIMER_300SEC						0x00000010
#define SW_AGE_TIMER_600SEC						0x00000020
#define SW_AGE_TIMER_1200SEC					0x00000030
#define SW_AGE_TIMER_2400SEC					0x00000040
#define SW_AGE_TIMER_4800SEC					0x00000050
#define SW_AGE_TIMER_9600SEC					0x00000060
#define SW_AGE_TIMER_19200SEC					0x00000070
//#define SW_AGE_TIMER_38400SEC					0x00000070

#define SW_BC_PREV_MASK							0x00000300
#define SW_BC_PREV_DISABLE						0
#define SW_BC_PREV_64BC							0x00000100
#define SW_BC_PREV_48BC							0x00000200
#define SW_BC_PREV_32BC							0x00000300

#define SW_MAX_LEN_MASK							0x00000C00
#define SW_MAX_LEN_1536							0
#define SW_MAX_LEN_1522							0x00000800
#define SW_MAX_LEN_1518							0x00000400

#define SW_DIS_COLABT							0x00001000

#define SW_HASH_ALG_MASK						0x00006000
#define SW_HASH_ALG_DIRECT						0
#define SW_HASH_ALG_XOR48						0x00002000
#define SW_HASH_ALG_XOR32						0x00004000

#define SW_DISABLE_BACKOFF_TIMER				0x00008000

#define SW_BP_NUM_MASK							0x000F0000
#define SW_BP_NUM_SHIFT							16
#define SW_BP_MODE_MASK							0x00300000
#define SW_BP_MODE_DISABLE						0
#define SW_BP_MODE_JAM							0x00100000
#define SW_BP_MODE_JAMALL						0x00200000
#define SW_BP_MODE_CARRIER						0x00300000
#define SW_RESRV_MC_FILTER						0x00400000
#define SW_BISR_DISABLE							0x00800000

#define SW_DIS_MII_WAS_TX						0x01000000
#define SW_BISS_EN								0x02000000
#define SW_BISS_TH_MASK							0x0C000000
#define SW_BISS_TH_SHIFT						26
#define SW_REQ_LATENCY_MASK						0xF0000000
#define SW_REQ_LATENCY_SHIFT					28


/* CPUp_conf_REG */
#define SW_CPU_PORT_DISABLE						0x00000001
#define SW_PADING_CRC							0x00000002
#define SW_BRIDGE_MODE							0x00000004

#define SW_DIS_UN_SHIFT							9
#define SW_DIS_UN_MASK							(0x3F << SW_DIS_UN_SHIFT)
#define SW_DIS_MC_SHIFT							16
#define SW_DIS_MC_MASK							(0x3F << SW_DIS_MC_SHIFT)
#define SW_DIS_BC_SHIFT							24
#define SW_DIS_BC_MASK							(0x3F << SW_DIS_BC_SHIFT)


/* Port_conf0_REG */
#define SW_DISABLE_PORT_MASK					0x0000003F
#define SW_EN_MC_MASK							0x00003F00
#define SW_EN_MC_SHIFT							8
#define SW_EN_BP_MASK							0x003F0000
#define SW_EN_BP_SHIFT							16
#define SW_EN_FC_MASK							0x3F000000
#define SW_EN_FC_SHIFT							24


/* Port_conf1_REG */
#define SW_DIS_SA_LEARN_MASK					0x0000003F
#define SW_PORT_BLOCKING_MASK					0x00000FC0
#define SW_PORT_BLOCKING_SHIFT					6
#define SW_PORT_BLOCKING_ON						0x1

#define SW_PORT_BLOCKING_MODE_MASK				0x0003F000
#define SW_PORT_BLOCKING_MODE_SHIFT				12
#define SW_PORT_BLOCKING_CTRLONLY				0x1

#define SW_EN_PORT_AGE_MASK						0x03F00000
#define SW_EN_PORT_AGE_SHIFT					20
#define SW_EN_SA_SECURED_MASK					0xFC000000
#define SW_EN_SA_SECURED_SHIFT					26


/* Port_conf2_REG */
#define SW_GMII_AN_EN							0x00000001
#define SW_GMII_FORCE_SPD_MASK					0x00000006
#define SW_GMII_FORCE_SPD_10M					0
#define SW_GMII_FORCE_SPD_100M					0x2
#define SW_GMII_FORCE_SPD_1000M					0x4

#define SW_GMII_FORCE_FULL_DUPLEX				0x00000008

#define SW_GMII_FORCE_RXFC						0x00000010
#define SW_GMII_FORCE_TXFC						0x00000020

#define SW_GMII_EN								0x00000040
#define SW_GMII_REVERSE							0x00000080

#define SW_GMII_TXC_CHECK_EN					0x00000100

#define SW_LED_FLASH_TIME_MASK					0x00030000
#define SW_LED_FLASH_TIME_30MS					0
#define SW_LED_FLASH_TIME_60MS					0x00010000
#define SW_LED_FLASH_TIME_240MS					0x00020000
#define SW_LED_FLASH_TIME_480MS					0x00030000