adm5120.h

Boot code for ADM5120 with serial console for Edimax router.

/*****************************************************************************
;
;   (C) Unpublished Work of ADMtek Incorporated.  All Rights Reserved.
;
;       THIS WORK IS AN UNPUBLISHED WORK AND CONTAINS CONFIDENTIAL,
;       PROPRIETARY AND TRADESECRET INFORMATION OF ADMTEK INCORPORATED.
;       ACCESS TO THIS WORK IS RESTRICTED TO (I) ADMTEK EMPLOYEES WHO HAVE A
;       NEED TO KNOW TO PERFORM TASKS WITHIN THE SCOPE OF THEIR ASSIGNMENTS
;       AND (II) ENTITIES OTHER THAN ADMTEK WHO HAVE ENTERED INTO APPROPRIATE
;       LICENSE AGREEMENTS.  NO PART OF THIS WORK MAY BE USED, PRACTICED,
;       PERFORMED, COPIED, DISTRIBUTED, REVISED, MODIFIED, TRANSLATED,
;       ABBRIDGED, CONDENSED, EXPANDED, COLLECTED, COMPILED, LINKED, RECAST,
;       TRANSFORMED OR ADAPTED WITHOUT THE PRIOR WRITTEN CONSENT OF ADMTEK.
;       ANY USE OR EXPLOITATION OF THIS WORK WITHOUT AUTHORIZATION COULD
;       SUBJECT THE PERPERTRATOR TO CRIMINAL AND CIVIL LIABILITY.
;
;------------------------------------------------------------------------------
;
;    Project : ADM5120
;    Creator : David Weng
;    File    : adm5120.h
;    Abstract: 
;
;Modification History:
; 
;
;*****************************************************************************/


#ifndef  __ADM5120_H__
#define  __ADM5120_H__


/*=========================  Physical Memory Map  ============================*/
#define ADM5120_SDRAM_BASE						0
#define ADM5120_SMEM1_BASE						0x10000000

#define ADM5120_EXTIO0_BASE						0x10C00000
#define ADM5120_EXTIO1_BASE						0x10E00000
#define ADM5120_MPMC_BASE						0x11000000
#define ADM5120_USBHOST_BASE					0x11200000
#define ADM5120_PCIMEM_BASE						0x11400000
#define ADM5120_PCIIO_BASE						0x11500000
#define ADM5120_PCICFG_BASE						0x115FFFF0
#define ADM5120_MIPS_BASE						0x11A00000
#define ADM5120_SWCTRL_BASE						0x12000000

#define ADM5120_INTC_BASE						0x12200000
#define ADM5120_SYSC_BASE						0x12400000

#define ADM5120_UART0_BASE						0x12600000
#define ADM5120_UART1_BASE						0x12800000

#define ADM5120_SMEM0_BASE						0x1FC00000


/*=======================  MIPS interrupt  ===================*/
#define ADM5120_MIPSINT_SOFT0					0
#define ADM5120_MIPSINT_SOFT1					1
#define ADM5120_MIPSINT_IRQ						2
#define ADM5120_MIPSINT_FIQ						3
#define ADM5120_MIPSINT_REV0					4
#define ADM5120_MIPSINT_REV1					5
#define ADM5120_MIPSINT_REV2					6
#define ADM5120_MIPSINT_TIMER					7



/*====================  MultiPort Memory Controller (MPMC) ==================*/
/* registers offset */
#define MPMC_CONTROL_REG						0x0000
#define MPMC_STATUS_REG							0x0004
#define MPMC_CONFIG_REG							0x0008

#define MPMC_DM_CONTROL_REG						0x0020
#define MPMC_DM_REFRESH_REG						0x0024

#define MPMC_DM_TRP_REG							0x0030
#define MPMC_DM_TRAS_REG						0x0034
#define MPMC_DM_TSREX_REG						0x0038
#define MPMC_DM_TAPR_REG						0x003C
#define MPMC_DM_TDAL_REG						0x0040
#define MPMC_DM_TWR_REG							0x0044
#define MPMC_DM_TRC_REG							0x0048
#define MPMC_DM_TRFC_REG						0x004C
#define MPMC_DM_TXSR_REG						0x0050
#define MPMC_DM_TRRD_REG						0x0054
#define MPMC_DM_TMRD_REG						0x0058

#define MPMC_SM_EXTWAIT_REG						0x0080

#define MPMC_DM_CONFIG0_REG						0x0100
#define MPMC_DM_RASCAS0_REG						0x0104

#define MPMC_DM_CONFIG1_REG						0x0120
#define MPMC_DM_RASCAS1_REG						0x0124

#define MPMC_SM_CONFIG0_REG						0x0200
#define MPMC_SM_WAITWEN0_REG					0x0204
#define MPMC_SM_WAITOEN0_REG					0x0208
#define MPMC_SM_WAITRD0_REG						0x020C
#define MPMC_SM_WAITPAGE0_REG					0x0210
#define MPMC_SM_WAITWR0_REG						0x0214
#define MPMC_SM_WAITTURN0_REG					0x0218

#define MPMC_SM_CONFIG1_REG						0x0220
#define MPMC_SM_WAITWEN1_REG					0x0224
#define MPMC_SM_WAITOEN1_REG					0x0228
#define MPMC_SM_WAITRD1_REG						0x022C
#define MPMC_SM_WAITPAGE1_REG					0x0230
#define MPMC_SM_WAITWR1_REG						0x0234
#define MPMC_SM_WAITTURN1_REG					0x0238

#define MPMC_SM_CONFIG2_REG						0x0240
#define MPMC_SM_WAITWEN2_REG					0x0244
#define MPMC_SM_WAITOEN2_REG					0x0248
#define MPMC_SM_WAITRD2_REG						0x024C
#define MPMC_SM_WAITPAGE2_REG					0x0250
#define MPMC_SM_WAITWR2_REG						0x0254
#define MPMC_SM_WAITTURN2_REG					0x0258

#define MPMC_SM_CONFIG3_REG						0x0260
#define MPMC_SM_WAITWEN3_REG					0x0264
#define MPMC_SM_WAITOEN3_REG					0x0268
#define MPMC_SM_WAITRD3_REG						0x026C
#define MPMC_SM_WAITPAGE3_REG					0x0270
#define MPMC_SM_WAITWR3_REG						0x0274
#define MPMC_SM_WAITTURN3_REG					0x0278

/* Macro for access MPMC register */
#define ADM5120_MPMC_REG(_offset)				\
		(*((volatile unsigned long *)(PA2VA(ADM5120_MPMC_BASE + (_offset)))))


/* MPMC_CONTROL_REG (offset: 0x0000) */
#define MPMC_DRAIN_W_BUF						0x00000008
#define MPMC_LOW_POWER_MODE						0x00000004
#define MPMC_ADDR_MIRROR						0x00000002
#define MPMC_ENABLE								0x00000001
#define MPMC_CONTROL_MASK						0x0000000f

/* MPMC_STATUS_REG (offset: 0x0004) */
#define MPMC_SREFACK							0x00000004
#define MPMC_WBUF_DIRTY							0x00000002
#define MPMC_BUSY								0x00000001
#define MPMC_STATUS_MASK						0x00000007

/* MPMC_CONFIG_REG (offset: 0x0008) */
#define MPMC_CLK_RATIO_1_1						0x00000000
#define MPMC_CLK_RATIO_1_2						0x00000100
#define MPMC_LITTLE_ENDIAN						0x00000000
#define MPMC_BIG_ENDIAN							0x00000001
#define MPMC_CONFIG_MASK						0x00000101

/* MPMC_DM_CONTROL_REG (offset: 0x0020) */
#define DM_PVHHOUT_HI_VOLTAGE					0x00008000
#define DM_RPOUT_HI_VOLTAGE						0x00004000
#define DM_DEEP_SLEEP_MODE						0x00002000

#define DM_SDRAM_NOP							0x00000180
#define DM_SDRAM_PRECHARGE_ALL					0x00000100
#define DM_SDRAM_MODE_SETTING					0x00000080
#define DM_SDRAM_NORMAL_OP						0x00000000
#define DM_SDRAM_OPMODE_MASK					0x00000180

#define DM_SELF_REFRESH_MODE					0x00000004
#define DM_CLKOUT_ALWAYS						0x00000002
#define DM_CLKEN_ALWAYS							0x00000001

#define MPMC_DM_CONTROL_MASK					0x0000e187


/* MPMC_DM_REFRESH_REG (offset:0x0024) */
#define MPMC_DM_REFRESH_MASK					0x00000300

/* MPMC_DM_TRP_REG (offset: 0x0030) */
#define MPMC_DM_TRP_MASK						0x0000000f

/* MPMC_DM_TRAS_REG (offset: 0x0034) */
#define MPMC_DM_TRAS_MASK						0x0000000f

/* MPMC_DM_TSREX_REG (offset: 0x0038) */
#define MPMC_DM_TSREX_MASK						0x0000000f

/* MPMC_DM_TAPR_REG	(offset: 0x003C) */
#define MPMC_DM_TAPR_MASK						0x0000000f

/* MPMC_DM_TDAL_REG	(offset: 0x0040) */
#define MPMC_DM_TDAL_MASK						0x0000000f

/* MPMC_DM_TWR_REG (offset: 0x0044) */
#define MPMC_DM_TWR_MASK						0x0000000f

/* MPMC_DM_TRC_REG (offset: 0x0048) */
#define MPMC_DM_TRC_MASK 						0x0000001f

/* MPMC_DM_TRFC_REG (offset: 0x004C) */
#define MPMC_DM_TRFC_MASK						0x0000001f

/* MPMC_DM_TXSR_REG	(offset: 0x0050) */
#define MPMC_DM_TXSR_MASK						0x0000001f

/* MPMC_DM_TRRD_REG	(offset: 0x0054) */
#define MPMC_DM_TRRD_MASK						0x0000000f

/* MPMC_DM_TMRD_REG	(offset: 0x0058) */
#define MPMC_DM_TMRD_MASK						0x0000000f

/* MPMC_SM_EXTWAIT_REG (offset:	0x0080) */
#define MPMC_SM_EXTWAIT_MASK					0x0000003f


/* MPMC_DM_CONFIG0_REG (offset: 0x0100) */
/* MPMC_DM_CONFIG1_REG (offset: 0x0120) */
#define DM_CFG_ROW_WIDTH_13BIT					0x20000000
#define DM_CFG_ROW_WIDTH_12BIT					0x10000000
#define DM_CFG_ROW_WIDTH_11BIT					0x00000000
#define DM_CFG_ROW_WIDTH_MASK					0x30000000
#define DM_CFG_ROW_WIDTH_SHIFT					28

#define DM_CFG_2BANK_DEV						0x00000000
#define DM_CFG_4BANK_DEV						0x04000000
#define DM_CFG_BANK_SHIFT						26

#define DM_CFG_COL_WIDTH_11BIT					0x01400000
#define DM_CFG_COL_WIDTH_10BIT					0x01000000
#define DM_CFG_COL_WIDTH_9BIT					0x00c00000
#define DM_CFG_COL_WIDTH_8BIT					0x00800000
#define DM_CFG_COL_WIDTH_7BIT					0x00400000
#define DM_CFG_COL_WIDTH_6BIT					0x00000000
#define DM_CFG_COL_WIDTH_MASK					0x01c00000
#define DM_CFG_COL_WIDTH_SHIFT					22

#define DM_CFG_WRITE_PROTECT					0x00100000
#define DM_CFG_BUFFER_EN						0x00080000

#define DM_CFG_ADDR_MAPPING_MASK				0x00005F80

#define DM_CFG_DEV_SYNC_FLASH					0x00000010
#define DM_CFG_DEV_LOWPOWER_SDRAM				0x00000008
#define DM_CFG_DEV_SDRAM						0x00000000
#define DM_CFG_DEV_MASK							0x00000018


/* MPMC_DM_RASCAS0_REG (offset: 0x0104) */
/* MPMC_DM_RASCAS1_REG (offset: 0x0124) */

#define DM_CAS_LATENCY_3						0x00000300
#define DM_CAS_LATENCY_2						0x00000200
#define DM_CAS_LATENCY_1						0x00000100

#define DM_RAS_LATENCY_3						0x00000003
#define DM_RAS_LATENCY_2						0x00000002
#define DM_RAS_LATENCY_1						0x00000001


/* MPMC_SM_CONFIG0_REG (offset: 0x0200) */
/* MPMC_SM_CONFIG1_REG (offset: 0x0220) */
/* MPMC_SM_CONFIG2_REG (offset: 0x0240) */
/* MPMC_SM_CONFIG3_REG (offset: 0x0260) */

#define SM_WRITE_PROTECT						0x00100000
#define SM_WRITEBUF_ENABLE						0x00080000
#define SM_EXTENDED_WAIT						0x00000100
#define SM_PB									0x00000080
#define SM_CS_HIGH								0x00000040
#define SM_PAGE_MODE							0x00000008

#define SM_MEM_WIDTH_32BIT						0x00000002
#define SM_MEM_WIDTH_16BIT						0x00000001
#define SM_MEM_WIDTH_8BIT						0x00000000
	
#define MPMC_SM_CONFIG_MASK						0x001801cb


/* MPMC_SM_WAITWEN0_REG	(offset: 0x0204) */
/* MPMC_SM_WAITWEN1_REG	(offset: 0x0224) */
/* MPMC_SM_WAITWEN2_REG	(offset: 0x0244) */
/* MPMC_SM_WAITWEN3_REG	(offset: 0x0264) */
#define MPMC_SM_WAITWEN_MASK					0x0000000f


/* MPMC_SM_WAITOEN0_REG (offset: 0x0208) */
/* MPMC_SM_WAITOEN1_REG (offset: 0x0228) */
/* MPMC_SM_WAITOEN2_REG (offset: 0x0248) */
/* MPMC_SM_WAITOEN3_REG (offset: 0x0268) */
#define MPMC_SM_WAITOEN_MASK					0x0000000f

/* MPMC_SM_WAITRD0_REG (offset: 0x020C) */
/* MPMC_SM_WAITRD1_REG (offset: 0x022C) */
/* MPMC_SM_WAITRD2_REG (offset: 0x024C) */
/* MPMC_SM_WAITRD3_REG (offset: 0x026C) */
#define MPMC_SM_WAITRD_MASK						0x0000001f

/* MPMC_SM_WAITPAGE0_REG (offset: 0x0210) */
/* MPMC_SM_WAITPAGE1_REG (offset: 0x0230) */
/* MPMC_SM_WAITPAGE2_REG (offset: 0x0250) */
/* MPMC_SM_WAITPAGE3_REG (offset: 0x0270) */
#define MPMC_SM_WAITPAGE_MASK					0x0000001f


/* MPMC_SM_WAITWR0_REG (offset: 0x0214) */
/* MPMC_SM_WAITWR1_REG (offset: 0x0234) */
/* MPMC_SM_WAITWR2_REG (offset: 0x0254) */
/* MPMC_SM_WAITWR3_REG (offset: 0x0274) */
#define MPMC_SM_WAITWR_MASK						0x0000001f


/* MPMC_SM_WAITTURN0_REG (offset: 0x0218) */
/* MPMC_SM_WAITTURN1_REG (offset: 0x0238) */
/* MPMC_SM_WAITTURN2_REG (offset: 0x0258) */
/* MPMC_SM_WAITTURN3_REG (offset: 0x0278) */
#define MPMC_SM_WAITTURN_MASK					0x0000000f


/* SDRAM mode register */
/* ref: SDRAM data sheet. Ex: Micron MT48LC4M16A2 data sheet. */
#define SDRAM_BTLEN_1							0x0000
#define SDRAM_BTLEN_2							0x0001
#define SDRAM_BTLEN_4							0x0002
#define SDRAM_BTLEN_8							0x0003
#define SDRAM_BTLEN_FULLPAGE					0x0007
#define SDRAM_BTLEN_MASK						0x0007

#define SDRAM_BT_SEQUENCIAL						0x0000
#define SDRAM_BT_INTERLEVED						0x0008

#define SDRAM_CAS_LATENCY_2						0x0020
#define SDRAM_CAS_LATENCY_3						0x0030
#define SDRAM_CAS_LATENCY_MASK					0x0030

#define SDRAM_OPMODE_STANDARD					0x0000
#define SDRAM_OPMODE_MASK						0x0180

#define SDRAM_WBTMODE_ENABLE					0x0000
#define SDRAM_WBTMODE_DISABLE					0x0200

#define SDRAM_MODEREG_MASK						0x03FF



/*==========================  Interrupt Controller  ==========================*/
/* registers offset */
#define IRQ_STATUS_REG							0x00	/* Read */
#define IRQ_RAW_STATUS_REG						0x04	/* Read */
#define IRQ_ENABLE_REG							0x08	/* Read/Write */
#define IRQ_DISABLE_REG							0x0C	/* Write */
#define IRQ_SOFT_REG							0x10	/* Write */