hw5120cfg.h

Boot code for ADM5120 with serial console for Edimax router.

// YES IT'S ENABLES
#if (HWPF_5120_SDRAM1_EN == OPTION_ENABLE)
#define HWPF_5120_SDRAM_BANK_NUM					2
#define HWPF_5120_SDRAM_CNTL						MEMCNTL_SDRAM1_EN
#else
#define HWPF_5120_SDRAM_CNTL						0
#define HWPF_5120_SDRAM_BANK_NUM					1
#define HWPF_5120_SDRAM_MEM_TOP_LIMIT				(HWPF_5120_SDRAM0_BASE + HWPF_5120_SDRAM0_SIZE)
#endif

// ++++++++++++++++++++++   SDRAM bank0 end   ++++++++++++++++++++++
//===========================================================================


//===========================================================================
// ++++++++++++++++++++++   SDRAM bank1 start   ++++++++++++++++++++++
#if (HWPF_5120_SDRAM_BANK_NUM == 2)

#ifndef HWPF_5120_SDRAM1_CAS_LATENCY
#error HWPF_5120_SDRAM1_CAS_LATENCY must be defined first!!
#endif  // HWPF_5120_SDRAM1_CAS_LATENCY

#ifndef HWPF_5120_SDRAM1_RAS_LATENCY
#error HWPF_5120_SDRAM1_RAS_LATENCY must be defined first!!
#endif	// HWPF_5120_SDRAM1_RAS_LATENCY


#if (HWPF_5120_SDRAM1_CAS_LATENCY == 2)
#define SDRAM1_CAS_LATENCY							SDRAM_CAS_LATENCY_2
#define MPMC_SDRAM1_CAS_LATENCY						DM_CAS_LATENCY_2
#elif (HWPF_5120_SDRAM1_CAS_LATENCY == 3)
#define SDRAM1_CAS_LATENCY							SDRAM_CAS_LATENCY_3
#define MPMC_SDRAM1_CAS_LATENCY						DM_CAS_LATENCY_3
#else
#error HWPF_5120_SDRAM1_CAS_LATENCY must be either 2 or 3!!
#endif

#if (HWPF_5120_SDRAM1_RAS_LATENCY == 1)
#define MPMC_SDRAM1_RAS_LATENCY						DM_RAS_LATENCY_1
#elif (HWPF_5120_SDRAM1_RAS_LATENCY == 2)
#define MPMC_SDRAM1_RAS_LATENCY						DM_RAS_LATENCY_2
#elif (HWPF_5120_SDRAM1_RAS_LATENCY == 3)
#define MPMC_SDRAM1_RAS_LATENCY						DM_RAS_LATENCY_3
#else
#error HWPF_5120_SDRAM1_RAS_LATENCY must be either 1, 2, or 3!!
#endif  // (HWPF_5120_SDRAM1_RAS_LATENCY == 1)

#define SDRAM_BANK1_RAS_CAS							(MPMC_SDRAM1_CAS_LATENCY \
													| MPMC_SDRAM1_RAS_LATENCY)



#if (HWPF_5120_SDRAM1_BUS_WIDTH != 32) && (HWPF_5120_SDRAM1_BUS_WIDTH != 16)
#error HWPF_5120_SDRAM1_BUS_WIDTH must be either 16 or 32
#endif

#if (HWPF_5120_SDRAM1_DEV_DATA_WIDTH != 8) && (HWPF_5120_SDRAM1_DEV_DATA_WIDTH != 16) && (HWPF_5120_SDRAM1_DEV_DATA_WIDTH != 32)
#error HWPF_5120_SDRAM1_DEV_DATA_WIDTH must be one of 8, 16, or 32.
#endif


#if HWPF_5120_SDRAM1_BUS_WIDTH == 16
	// 16Bits Bus
	#if HWPF_5120_SDRAM1_DEV_DATA_WIDTH == 32
		#error HWPF_5120_SDRAM1_DEV_DATA_WIDTH is larger than HWPF_5120_SDRAM1_DEV_DATA_WIDTH!!
	#endif

	#define SDRAM1_BURST_LEN						SDRAM_BTLEN_8
	#define MPMC_SDRAM1_AM14						0

	
	#if HWPF_5120_SDRAM1_DEV_SIZE == 16
		#define MPMC_SDRAM1_AM11_9					0
		#if HWPF_5120_SDRAM1_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK1_SIZE				4
			#define SDRAM_BANK1_MODE_SHIFT			12
			#define MPMC_SDRAM1_AM8_7				0
			#define MPMC_SDRAM1_NB					DM_CFG_2BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_11BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_9BIT
		#else
			#define SDRAM_BANK1_SIZE				2
			#define SDRAM_BANK1_MODE_SHIFT			10
			#define MPMC_SDRAM1_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM1_NB					DM_CFG_2BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_11BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_8BIT
		#endif
	#elif HWPF_5120_SDRAM1_DEV_SIZE == 64
		#define MPMC_SDRAM1_AM11_9					(0x1 << 9)
		#if HWPF_5120_SDRAM1_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK1_SIZE				16
			#define SDRAM_BANK1_MODE_SHIFT			12
			#define MPMC_SDRAM1_AM8_7				0
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_12BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_9BIT
		#else
			#define SDRAM_BANK1_SIZE				8
			#define SDRAM_BANK1_MODE_SHIFT			11
			#define MPMC_SDRAM1_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_12BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_8BIT
		#endif
	#elif HWPF_5120_SDRAM1_DEV_SIZE == 128
		#define MPMC_SDRAM1_AM11_9					(0x2 << 9)
		#if HWPF_5120_SDRAM1_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK1_SIZE				32
			#define SDRAM_BANK1_MODE_SHIFT			13
			#define MPMC_SDRAM1_AM8_7				0
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_12BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_10BIT
		#else
			#define SDRAM_BANK1_SIZE				16
			#define SDRAM_BANK1_MODE_SHIFT			12
			#define MPMC_SDRAM1_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_12BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_9BIT
		#endif
	#elif HWPF_5120_SDRAM1_DEV_SIZE == 256
		#define MPMC_SDRAM1_AM11_9					(0x3 << 9)
		#if HWPF_5120_SDRAM1_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK1_SIZE				64
			#define SDRAM_BANK1_MODE_SHIFT			13
			#define MPMC_SDRAM1_AM8_7				0
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_10BIT
		#else
			#define SDRAM_BANK1_SIZE				32
			#define SDRAM_BANK1_MODE_SHIFT			12
			#define MPMC_SDRAM1_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_9BIT
		#endif
	#elif HWPF_5120_SDRAM1_DEV_SIZE == 512
		#define MPMC_SDRAM1_AM11_9					(0x4 << 9)
		#if HWPF_5120_SDRAM1_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK1_SIZE				128
			#define SDRAM_BANK1_MODE_SHIFT			14
			#define MPMC_SDRAM1_AM8_7				(0x0 << 7)
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_11BIT
		#else
			#define SDRAM_BANK1_SIZE				64
			#define SDRAM_BANK1_MODE_SHIFT			13
			#define MPMC_SDRAM1_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_10BIT
		#endif
	#else
		#error HWPF_5120_SDRAM1_DEV_SIZE must be one of 16, 64, 128, 256, or 512!!
	#endif


#else
	// 32 bits Bus
	#define SDRAM1_BURST_LEN						SDRAM_BTLEN_4
	#define MPMC_SDRAM1_AM14						(0x1<<14)
	
	#if HWPF_5120_SDRAM1_DEV_SIZE == 16
		#define MPMC_SDRAM1_AM11_9					0
		#if HWPF_5120_SDRAM1_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK1_SIZE				8
			#define SDRAM_BANK1_MODE_SHIFT			12
			#define MPMC_SDRAM1_AM8_7				0
			#define MPMC_SDRAM1_NB					DM_CFG_2BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_11BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_9BIT
		#elif HWPF_5120_SDRAM1_DEV_DATA_WIDTH == 16
			#define SDRAM_BANK1_SIZE				4
			#define SDRAM_BANK1_MODE_SHIFT			11
			#define MPMC_SDRAM1_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM1_NB					DM_CFG_2BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_11BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_8BIT
		#else
			#error 512Kx32 SDRAM is not supported.
		#endif
	#elif HWPF_5120_SDRAM1_DEV_SIZE == 64
		#define MPMC_SDRAM1_AM11_9					(0x1 << 9)
		#if HWPF_5120_SDRAM1_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK1_SIZE				32
			#define SDRAM_BANK1_MODE_SHIFT			13
			#define MPMC_SDRAM1_AM8_7				0
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_12BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_9BIT
		#elif HWPF_5120_SDRAM1_DEV_DATA_WIDTH == 16
			#define SDRAM_BANK1_SIZE				16
			#define SDRAM_BANK1_MODE_SHIFT			12
			#define MPMC_SDRAM1_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_12BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_8BIT
		#else
			#define SDRAM_BANK1_SIZE				8
			#define SDRAM_BANK1_MODE_SHIFT			12
			#define MPMC_SDRAM1_AM8_7				(0x2 << 7)
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_11BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_8BIT
		#endif
	#elif HWPF_5120_SDRAM1_DEV_SIZE == 128
		#define MPMC_SDRAM1_AM11_9					(0x2 << 9)
		#if HWPF_5120_SDRAM1_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK1_SIZE				64
			#define SDRAM_BANK1_MODE_SHIFT			14
			#define MPMC_SDRAM1_AM8_7				0
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_12BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_10BIT
		#elif HWPF_5120_SDRAM1_DEV_DATA_WIDTH == 16
		// DE THESE ARE THE VALUES ACTUALLY ON THE H2WR54G AS SHIPPED BY HAWKING
		// Actually that may not be true...
		// I'm changing 32 to 16 on the next line...
		//	#define SDRAM_BANK1_SIZE				32
		// Will check the binary output.
			#define SDRAM_BANK1_SIZE				16
			#define SDRAM_BANK1_MODE_SHIFT			13
			#define MPMC_SDRAM1_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_12BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_9BIT
		#else
			#define SDRAM_BANK1_SIZE				16
			#define SDRAM_BANK1_MODE_SHIFT			12
			#define MPMC_SDRAM1_AM8_7				(0x2 << 7)
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_12BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_8BIT
		#endif
	#elif HWPF_5120_SDRAM1_DEV_SIZE == 256
		#define MPMC_SDRAM1_AM11_9					(0x3 << 9)
		#if HWPF_5120_SDRAM1_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK1_SIZE				128
			#define SDRAM_BANK1_MODE_SHIFT			14
			#define MPMC_SDRAM1_AM8_7				0
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_10BIT
		#elif HWPF_5120_SDRAM1_DEV_DATA_WIDTH == 16
			#define SDRAM_BANK1_SIZE				64
			#define SDRAM_BANK1_MODE_SHIFT			13
			#define MPMC_SDRAM1_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_9BIT
		#else
			#define SDRAM_BANK1_SIZE				32
			#define SDRAM_BANK1_MODE_SHIFT			12
			#define MPMC_SDRAM1_AM8_7				(0x2 << 7)
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_8BIT
		#endif
	#elif HWPF_5120_SDRAM1_DEV_SIZE == 512
		#define MPMC_SDRAM1_AM11_9					(0x4 << 9)
		#if HWPF_5120_SDRAM1_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK1_SIZE				256
			#define SDRAM_BANK1_MODE_SHIFT			15
			#define MPMC_SDRAM1_AM8_7				(0x0 << 7)
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_11BIT
		#elif HWPF_5120_SDRAM1_DEV_DATA_WIDTH == 16
			#define SDRAM_BANK1_SIZE				128
			#define SDRAM_BANK1_MODE_SHIFT			14
			#define MPMC_SDRAM1_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM1_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM1_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM1_CW					DM_CFG_COL_WIDTH_10BIT
		#else
			#error 16Mx32 SDRAM is not supported.
		#endif
	#else
		#error HWPF_5120_SDRAM1_DEV_SIZE must be one of 16, 64, 128, 256, or 512!!
	#endif
#endif


#define SDRAM_BANK1_MODE 							(SDRAM1_BURST_LEN		\
													| SDRAM1_CAS_LATENCY	\
													| SDRAM_OPMODE_STANDARD \
													| SDRAM_WBTMODE_ENABLE)



#define MPMC_SDRAM_BANK1_CFG						(MPMC_SDRAM1_NB 		\
													| MPMC_SDRAM1_RW 		\
													| MPMC_SDRAM1_CW		\
													| MPMC_SDRAM1_AM14		\
													| MPMC_SDRAM1_AM11_9	\
													| MPMC_SDRAM1_AM8_7)

#if SDRAM_BANK1_SIZE == 4
	#define MEM_SDRAM1_SIZE							SDRAM_SIZE_4MBYTES
#elif SDRAM_BANK1_SIZE == 8
	#define MEM_SDRAM1_SIZE							SDRAM_SIZE_8MBYTES
#elif SDRAM_BANK1_SIZE == 16
	#define MEM_SDRAM1_SIZE							SDRAM_SIZE_16MBYTES
#elif SDRAM_BANK1_SIZE == 64
	#define MEM_SDRAM1_SIZE							SDRAM_SIZE_64MBYTES
#elif SDRAM_BANK1_SIZE == 128
	#define MEM_SDRAM1_SIZE							SDRAM_SIZE_128MBYTES
#else
	#error SDRAM bank1 configuration error!!
#endif

#if SDRAM_BANK1_SIZE != SDRAM_BANK0_SIZE
	#error SDRAM_BANK1_SIZE must be equal to SDRAM_BANK0_SIZE!!!
#endif

#define HWPF_5120_SDRAM1_BASE						(HWPF_5120_SDRAM0_BASE + HWPF_5120_SDRAM0_SIZE)
#define HWPF_5120_SDRAM1_SIZE						(SDRAM_BANK1_SIZE << 20)

#define HWPF_5120_SDRAM_MEM_TOP_LIMIT				(HWPF_5120_SDRAM1_BASE + HWPF_5120_SDRAM1_SIZE)
#endif	// (HWPF_5120_SDRAM_BANK_NUM == 2)

#define HWPF_5120_DRAM_END							HWPF_5120_SDRAM_MEM_TOP_LIMIT

// ++++++++++++++++++++++   SDRAM bank1 end   ++++++++++++++++++++++

// ++++++++++++++++++++   SDRAM Timing start   +++++++++++++++++++++
#if (HWPF_5120_SDRAM_tRP < 0) || (HWPF_5120_SDRAM_tRP > 15)
#error HWPF_5120_SDRAM_tRP is out of range!!!
#endif

#if (HWPF_5120_SDRAM_tRAS < 0) || (HWPF_5120_SDRAM_tRAS > 15)
#error HWPF_5120_SDRAM_tRAS is out of range!!!
#endif

#if (HWPF_5120_SDRAM_tSREX < 0) || (HWPF_5120_SDRAM_tSREX > 15)
#error HWPF_5120_SDRAM_tSREX is out of range!!!
#endif

#if (HWPF_5120_SDRAM_tAPR < 0) || (HWPF_5120_SDRAM_tAPR > 15)
#error HWPF_5120_SDRAM_tAPR is out of range!!!
#endif

#if (HWPF_5120_SDRAM_tDAL < 0) || (HWPF_5120_SDRAM_tDAL > 15)
#error HWPF_5120_SDRAM_tDAL is out of range!!!
#endif

#if (HWPF_5120_SDRAM_tWR < 0) || (HWPF_5120_SDRAM_tWR > 15)
#error HWPF_5120_SDRAM_tWR is out of range!!!
#endif

#if (HWPF_5120_SDRAM_tRC < 0) || (HWPF_5120_SDRAM_tRC > 31)
#error HWPF_5120_SDRAM_tRC is out of range!!!
#endif