hw5120cfg.h

Boot code for ADM5120 with serial console for Edimax router.

#else
#error The value of HWPF_5120_SMEM1_PAGE_MODE must be either OPTION_ENABLE or OPTION_DISABLE!!!
#endif  // (HWPF_5120_SMEM1_PAGE_MODE == 1)

#if (HWPF_5120_SMEM1_CS_TO_WE_WAIT < 0) || (HWPF_5120_SMEM1_CS_TO_WE_WAIT > 15)
#error HWPF_5120_SMEM1_CS_TO_WE_WAIT is out of range!!!
#endif

#if (HWPF_5120_SMEM1_CS_TO_OE_WAIT < 0) || (HWPF_5120_SMEM1_CS_TO_OE_WAIT > 15)
#error HWPF_5120_SMEM1_CS_TO_OE_WAIT is out of range!!!
#endif

#if (HWPF_5120_SMEM1_READ_WAIT < 0) || (HWPF_5120_SMEM1_READ_WAIT > 31)
#error HWPF_5120_SMEM1_READ_WAIT is out of range!!!
#endif

#if (HWPF_5120_SMEM1_WRITE_WAIT < 0) || (HWPF_5120_SMEM1_WRITE_WAIT >31)
#error HWPF_5120_SMEM1_WRITE_WAIT is out of range!!!
#endif

#if (HWPF_5120_SMEM1_TURN_WAIT < 0) || (HWPF_5120_SMEM1_TURN_WAIT > 15)
#error HWPF_5120_SMEM1_TURN_WAIT is out of range!!!
#endif


#define SMEM1_CFG									( SMEM1_BUS_WIDTH 		\
													| SMEM1_CS_POLARITY 	\
													| SMEM1_PM_MODE 		\
													| SMEM1_PB)



#define SmemBank1_Config							SMEM1_CFG
#define	SmemBank1_WaitWen							HWPF_5120_SMEM1_CS_TO_WE_WAIT
#define	SmemBank1_WaitOen							HWPF_5120_SMEM1_CS_TO_OE_WAIT
#define	SmemBank1_WaitRd							HWPF_5120_SMEM1_READ_WAIT
#define	SmemBank1_WaitPage							31
#define	SmemBank1_WaitWr							HWPF_5120_SMEM1_WRITE_WAIT
#define	SmemBank1_WaitTurn							HWPF_5120_SMEM1_TURN_WAIT


#define HWPF_5120_FLASH_BANK_NUM					2

#define HWPF_5120_ROMSIZE_CFG						( (SMEM0_BANK_SIZE << ROM0_SIZE_SHIFT)	\
													| (SMEM1_BANK_SIZE << ROM1_SIZE_SHIFT))

#else	// (HWPF_5120_SMEM1_EN == OPTION_ENABLE)
#define HWPF_5120_FLASH_BANK_NUM					1
#define HWPF_5120_ROMSIZE_CFG						( (SMEM0_BANK_SIZE << ROM0_SIZE_SHIFT)	\
													| (ROM_SIZE_DISABLE << ROM1_SIZE_SHIFT))
#endif	// ! (HWPF_5120_SMEM1_EN == OPTION_ENABLE)
// ++++++++++++++++++++++   SMEM bank1 end   ++++++++++++++++++++++

//===========================================================================


//===========================================================================
// ++++++++++++++++++++++   SDRAM bank0 start   ++++++++++++++++++++++
// SDRAM bank 0 configuration 
#ifndef HWPF_5120_SDRAM0_CAS_LATENCY
#error HWPF_5120_SDRAM0_CAS_LATENCY must be defined first!!
#endif

#ifndef HWPF_5120_SDRAM0_RAS_LATENCY
#error HWPF_5120_SDRAM0_RAS_LATENCY must be defined first!!
#endif


#if (HWPF_5120_SDRAM0_CAS_LATENCY == 2)
#define SDRAM0_CAS_LATENCY							SDRAM_CAS_LATENCY_2
#define MPMC_SDRAM0_CAS_LATENCY						DM_CAS_LATENCY_2
#elif (HWPF_5120_SDRAM0_CAS_LATENCY == 3)
#define SDRAM0_CAS_LATENCY							SDRAM_CAS_LATENCY_3
#define MPMC_SDRAM0_CAS_LATENCY						DM_CAS_LATENCY_3
#else
#error HWPF_5120_SDRAM0_CAS_LATENCY must be either 2 or 3!!
#endif

#if (HWPF_5120_SDRAM0_RAS_LATENCY == 1)
#define MPMC_SDRAM0_RAS_LATENCY						DM_RAS_LATENCY_1
#elif (HWPF_5120_SDRAM0_RAS_LATENCY == 2)
#define MPMC_SDRAM0_RAS_LATENCY						DM_RAS_LATENCY_2
#elif (HWPF_5120_SDRAM0_RAS_LATENCY == 3)
#define MPMC_SDRAM0_RAS_LATENCY						DM_RAS_LATENCY_3
#else
#error HWPF_5120_SDRAM0_RAS_LATENCY must be either 1, 2, or 3!!
#endif  // (HWPF_5120_SDRAM0_RAS_LATENCY == 1)

#define SDRAM_BANK0_RAS_CAS							(MPMC_SDRAM0_CAS_LATENCY 	\
													| MPMC_SDRAM0_RAS_LATENCY)


#if (HWPF_5120_SDRAM0_BUS_WIDTH != 32) && (HWPF_5120_SDRAM0_BUS_WIDTH != 16)
#error HWPF_5120_SDRAM0_BUS_WIDTH must be either 16 or 32
#endif

#if (HWPF_5120_SDRAM0_DEV_DATA_WIDTH != 8) && (HWPF_5120_SDRAM0_DEV_DATA_WIDTH != 16) && (HWPF_5120_SDRAM0_DEV_DATA_WIDTH != 32)
#error HWPF_5120_SDRAM0_DEV_DATA_WIDTH must be one of 8, 16, or 32.
#endif


#if HWPF_5120_SDRAM0_BUS_WIDTH == 16
	// 16Bits Bus
	#if HWPF_5120_SDRAM0_DEV_DATA_WIDTH == 32
		#error HWPF_5120_SDRAM0_DEV_DATA_WIDTH is larger than HWPF_5120_SDRAM0_DEV_DATA_WIDTH!!
	#endif

	#define SDRAM0_BURST_LEN						SDRAM_BTLEN_8
	#define MPMC_SDRAM0_AM14						0

	
	#if HWPF_5120_SDRAM0_DEV_SIZE == 16
		#define MPMC_SDRAM0_AM11_9					0
		#if HWPF_5120_SDRAM0_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK0_SIZE				4
			#define SDRAM_BANK0_MODE_SHIFT			12
			#define MPMC_SDRAM0_AM8_7				0
			#define MPMC_SDRAM0_NB					DM_CFG_2BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_11BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_9BIT
		#else
			#define SDRAM_BANK0_SIZE				2
			#define SDRAM_BANK0_MODE_SHIFT			10
			#define MPMC_SDRAM0_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM0_NB					DM_CFG_2BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_11BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_8BIT
		#endif
	#elif HWPF_5120_SDRAM0_DEV_SIZE == 64
		#define MPMC_SDRAM0_AM11_9					(0x1 << 9)
		#if HWPF_5120_SDRAM0_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK0_SIZE				16
			#define SDRAM_BANK0_MODE_SHIFT			12
			#define MPMC_SDRAM0_AM8_7				0
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_12BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_9BIT
		#else
			#define SDRAM_BANK0_SIZE				8
			#define SDRAM_BANK0_MODE_SHIFT			11
			#define MPMC_SDRAM0_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_12BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_8BIT
		#endif
	#elif HWPF_5120_SDRAM0_DEV_SIZE == 128
		#define MPMC_SDRAM0_AM11_9					(0x2 << 9)
		#if HWPF_5120_SDRAM0_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK0_SIZE				32
			#define SDRAM_BANK0_MODE_SHIFT			13
			#define MPMC_SDRAM0_AM8_7				0
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_12BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_10BIT
		#else
			#define SDRAM_BANK0_SIZE				16
			#define SDRAM_BANK0_MODE_SHIFT			12
			#define MPMC_SDRAM0_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_12BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_9BIT
		#endif
	#elif HWPF_5120_SDRAM0_DEV_SIZE == 256
		#define MPMC_SDRAM0_AM11_9					(0x3 << 9)
		#if HWPF_5120_SDRAM0_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK0_SIZE				64
			#define SDRAM_BANK0_MODE_SHIFT			13
			#define MPMC_SDRAM0_AM8_7				0
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_10BIT
		#else
			#define SDRAM_BANK0_SIZE				32
			#define SDRAM_BANK0_MODE_SHIFT			12
			#define MPMC_SDRAM0_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_9BIT
		#endif
	#elif HWPF_5120_SDRAM0_DEV_SIZE == 512
		#define MPMC_SDRAM0_AM11_9					(0x4 << 9)
		#if HWPF_5120_SDRAM0_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK0_SIZE				128
			#define SDRAM_BANK0_MODE_SHIFT			14
			#define MPMC_SDRAM0_AM8_7				(0x0 << 7)
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_11BIT
		#else
			#define SDRAM_BANK0_SIZE				64
			#define SDRAM_BANK0_MODE_SHIFT			13
			#define MPMC_SDRAM0_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_10BIT
		#endif
	#else
		#error HWPF_5120_SDRAM0_DEV_SIZE must be one of 16, 64, 128, 256, or 512!!
	#endif


#else
	// 32 bits Bus
	#define SDRAM0_BURST_LEN						SDRAM_BTLEN_4
	#define MPMC_SDRAM0_AM14						(0x1<<14)
	
	#if HWPF_5120_SDRAM0_DEV_SIZE == 16
		#define MPMC_SDRAM0_AM11_9					0
		#if HWPF_5120_SDRAM0_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK0_SIZE				8
			#define SDRAM_BANK0_MODE_SHIFT			12
			#define MPMC_SDRAM0_AM8_7				0
			#define MPMC_SDRAM0_NB					DM_CFG_2BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_11BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_9BIT
		#elif HWPF_5120_SDRAM0_DEV_DATA_WIDTH == 16
			#define SDRAM_BANK0_SIZE				4
			#define SDRAM_BANK0_MODE_SHIFT			11
			#define MPMC_SDRAM0_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM0_NB					DM_CFG_2BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_11BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_8BIT
		#else
			#error 512Kx32 SDRAM is not supported.
		#endif
	#elif HWPF_5120_SDRAM0_DEV_SIZE == 64
		#define MPMC_SDRAM0_AM11_9					(0x1 << 9)
		#if HWPF_5120_SDRAM0_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK0_SIZE				32
			#define SDRAM_BANK0_MODE_SHIFT			13
			#define MPMC_SDRAM0_AM8_7				0
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_12BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_9BIT
		#elif HWPF_5120_SDRAM0_DEV_DATA_WIDTH == 16
			#define SDRAM_BANK0_SIZE				16
			#define SDRAM_BANK0_MODE_SHIFT			12
			#define MPMC_SDRAM0_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_12BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_8BIT
		#else
			#define SDRAM_BANK0_SIZE				8
			#define SDRAM_BANK0_MODE_SHIFT			12
			#define MPMC_SDRAM0_AM8_7				(0x2 << 7)
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_11BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_8BIT
		#endif
	#elif HWPF_5120_SDRAM0_DEV_SIZE == 128
		#define MPMC_SDRAM0_AM11_9					(0x2 << 9)
		#if HWPF_5120_SDRAM0_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK0_SIZE				64
			#define SDRAM_BANK0_MODE_SHIFT			14
			#define MPMC_SDRAM0_AM8_7				0
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_12BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_10BIT
		#elif HWPF_5120_SDRAM0_DEV_DATA_WIDTH == 16
		// DE THESE ARE THE VALUES ACTUALLY ON THE H2WR54G AS SHIPPED BY HAWKING
		// Actually that may not be true...
		// I'm changing 32 to 16 on the next line because
		// THERE IS NO 8 MBYTE SDRAM SIZE SETTING ON THE ADM5120!!!
		//	#define SDRAM_BANK0_SIZE				32
			#define SDRAM_BANK0_SIZE				16
			#define SDRAM_BANK0_MODE_SHIFT			13
			#define MPMC_SDRAM0_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_12BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_9BIT
		#else
			#define SDRAM_BANK0_SIZE				16
			#define SDRAM_BANK0_MODE_SHIFT			12
			#define MPMC_SDRAM0_AM8_7				(0x2 << 7)
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_8BIT
		#endif
	#elif HWPF_5120_SDRAM0_DEV_SIZE == 256
		#define MPMC_SDRAM0_AM11_9					(0x3 << 9)
		#if HWPF_5120_SDRAM0_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK0_SIZE				128
			#define SDRAM_BANK0_MODE_SHIFT			14
			#define MPMC_SDRAM0_AM8_7				0
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_10BIT
		#elif HWPF_5120_SDRAM0_DEV_DATA_WIDTH == 16
			#define SDRAM_BANK0_SIZE				64
			#define SDRAM_BANK0_MODE_SHIFT			13
			#define MPMC_SDRAM0_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_9BIT
		#else
			#define SDRAM_BANK0_SIZE				32
			#define SDRAM_BANK0_MODE_SHIFT			12
			#define MPMC_SDRAM0_AM8_7				(0x2 << 7)
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_8BIT
		#endif
	#elif HWPF_5120_SDRAM0_DEV_SIZE == 512
		#define MPMC_SDRAM0_AM11_9					(0x4 << 9)
		#if HWPF_5120_SDRAM0_DEV_DATA_WIDTH == 8
			#define SDRAM_BANK0_SIZE				256
			#define SDRAM_BANK0_MODE_SHIFT			15
			#define MPMC_SDRAM0_AM8_7				(0x0 << 7)
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_11BIT
		#elif HWPF_5120_SDRAM0_DEV_DATA_WIDTH == 16
			#define SDRAM_BANK0_SIZE				128
			#define SDRAM_BANK0_MODE_SHIFT			14
			#define MPMC_SDRAM0_AM8_7				(0x1 << 7)
			#define MPMC_SDRAM0_NB					DM_CFG_4BANK_DEV
			#define MPMC_SDRAM0_RW					DM_CFG_ROW_WIDTH_13BIT
			#define MPMC_SDRAM0_CW					DM_CFG_COL_WIDTH_10BIT
		#else
			#error 16Mx32 SDRAM is not supported.
		#endif
	#else
		#error HWPF_5120_SDRAM0_DEV_SIZE must be one of 16, 64, 128, 256, or 512!!
	#endif
#endif


#define SDRAM_BANK0_MODE 							(SDRAM0_BURST_LEN		\
													| SDRAM0_CAS_LATENCY	\
													| SDRAM_OPMODE_STANDARD \
													| SDRAM_WBTMODE_ENABLE)



#define MPMC_SDRAM_BANK0_CFG						(MPMC_SDRAM0_NB 		\
													| MPMC_SDRAM0_RW 		\
													| MPMC_SDRAM0_CW		\
													| MPMC_SDRAM0_AM14		\
													| MPMC_SDRAM0_AM11_9	\
													| MPMC_SDRAM0_AM8_7)

#if SDRAM_BANK0_SIZE == 4
	#define HWPF_5120_SDRAMSIZE_CFG				SDRAM_SIZE_4MBYTES
#elif SDRAM_BANK0_SIZE == 8
	#define HWPF_5120_SDRAMSIZE_CFG				SDRAM_SIZE_8MBYTES
#elif SDRAM_BANK0_SIZE == 16
	#define HWPF_5120_SDRAMSIZE_CFG				SDRAM_SIZE_16MBYTES
#elif SDRAM_BANK0_SIZE == 64
	#define HWPF_5120_SDRAMSIZE_CFG				SDRAM_SIZE_64MBYTES
#elif SDRAM_BANK0_SIZE == 128
	#define HWPF_5120_SDRAMSIZE_CFG				SDRAM_SIZE_128MBYTES
#else
	#error SDRAM bank0 configuration error!!
#endif


#define HWPF_5120_SDRAM0_BASE						ADM5120_SDRAM_BASE
#define HWPF_5120_SDRAM0_SIZE						(SDRAM_BANK0_SIZE << 20)