📄 hw5120cfg.h
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#define HWPF_5120_EXTIO1_INT_POLARITY 0// Enable wait control// This OPTION is ORed with HWPF_5120_EXTIO0_WAIT_EN!!#define HWPF_5120_EXTIO1_WAIT_EN OPTION_DISABLE// Bus width of Ext I/o bank 0. (legal value are 8, 16 and 32)#define HWPF_5120_EXTIO1_BUS_WIDTH 16// Device data bus width of Ext I/o bank 0. (legal value are 8, 16 and 32)#define HWPF_5120_EXTIO1_DEV_WIDTH 16// Chip select polarity [legal value are 0(low active) and 1(high active)]#define HWPF_5120_EXTIO1_CS_POLARITY 0// Asyn page mode [legal value are OPTION_DISABLE and OPTION_ENABLE]#define HWPF_5120_EXTIO1_PAGE_MODE OPTION_DISABLE// Chip select to Output enable wait state: // (HWPF_5120_SMEM0_CS_TO_OE_WAIT) wait state will be inserted.// Unit: clock, range [0-15]#define HWPF_5120_EXTIO1_CS_TO_OE_WAIT 0// Read Wait state. (HWPF_5120_EXTIO0_READ_WAIT + 1) wait state will be inserted.// Unit: clock, range [0-31]#define HWPF_5120_EXTIO1_READ_WAIT 9// Chip select to Write enable wait state: // (HWPF_5120_EXTIO0_CS_TO_WE_WAIT + 1) wait state will be inserted.// Unit: clock, range [0-15]#define HWPF_5120_EXTIO1_CS_TO_WE_WAIT 0// Write Wait state. (HWPF_5120_EXTIO0_WRITE_WAIT + 2) wait state will be inserted.// Unit: clock, range [0-31]#define HWPF_5120_EXTIO1_WRITE_WAIT 9// Bus turnaround Wait state. (HWPF_5120_EXTIO0_TURN_WAIT + 1) wait state will be inserted.// Unit: clock, range [0-15]#define HWPF_5120_EXTIO1_TURN_WAIT 1// Ext I/O bank 0 end//******************************************************//***************************************************************************// Ext I/O configuration sections end//***************************************************************************//***************************************************************************// GPIO configuration sections start//***************************************************************************// GPIO0_INPUT_MODE/GPIO0_OUTPUT_MODE#define HWPF_5120_GPIO0_MODE GPIO0_INPUT_MODE// GPIO0_OUTPUT_LOW/GPIO0_OUTPUT_HI#define HWPF_5120_GPIO0_DEFOUT GPIO0_OUTPUT_LOW// GPIO1_INPUT_MODE/GPIO1_OUTPUT_MODE#define HWPF_5120_GPIO1_MODE GPIO1_INPUT_MODE// GPIO1_OUTPUT_LOW/GPIO1_OUTPUT_HI#define HWPF_5120_GPIO1_DEFOUT GPIO1_OUTPUT_LOW// GPIO2_INPUT_MODE/GPIO2_OUTPUT_MODE#define HWPF_5120_GPIO2_MODE GPIO2_INPUT_MODE// GPIO2_OUTPUT_LOW/GPIO2_OUTPUT_HI#define HWPF_5120_GPIO2_DEFOUT GPIO2_OUTPUT_LOW// GPIO3_INPUT_MODE/GPIO2_OUTPUT_MODE#define HWPF_5120_GPIO3_MODE GPIO3_INPUT_MODE// GPIO3_OUTPUT_LOW/GPIO3_OUTPUT_HI#define HWPF_5120_GPIO3_DEFOUT GPIO3_OUTPUT_LOW// GPIO4_INPUT_MODE/GPIO4_OUTPUT_MODE#define HWPF_5120_GPIO4_MODE GPIO4_INPUT_MODE// GPIO4_OUTPUT_LOW/GPIO4_OUTPUT_HI#define HWPF_5120_GPIO4_DEFOUT GPIO4_OUTPUT_LOW// GPIO5_INPUT_MODE/GPIO5_OUTPUT_MODE#define HWPF_5120_GPIO5_MODE GPIO5_INPUT_MODE// GPIO5_OUTPUT_LOW/GPIO5_OUTPUT_HI#define HWPF_5120_GPIO5_DEFOUT GPIO5_OUTPUT_LOW// GPIO6_INPUT_MODE/GPIO6_OUTPUT_MODE#define HWPF_5120_GPIO6_MODE GPIO6_INPUT_MODE// GPIO6_OUTPUT_LOW/GPIO6_OUTPUT_HI#define HWPF_5120_GPIO6_DEFOUT GPIO6_OUTPUT_LOW// GPIO7_INPUT_MODE/GPIO7_OUTPUT_MODE#define HWPF_5120_GPIO7_MODE GPIO7_INPUT_MODE// GPIO7_OUTPUT_LOW/GPIO7_OUTPUT_HI#define HWPF_5120_GPIO7_DEFOUT GPIO7_OUTPUT_LOW//***************************************************************************// GPIO configuration sections end//***************************************************************************//***************************************************************************// PORT LED configuration sections start//***************************************************************************/* Available options are listed below GPIOL_INPUT_MODE GPIOL_OUTPUT_FLASH GPIOL_OUTPUT_LOW GPIOL_OUTPUT_HIGH GPIOL_LINK_LED GPIOL_SPEED_LED GPIOL_DUPLEX_LED GPIOL_ACT_LED GPIOL_COL_LED GPIOL_LINK_ACT_LED GPIOL_DUPLEX_COL_LED GPIOL_10MLINK_ACT_LED GPIOL_100MLINK_ACT_LED*///******************************************************// PORT0 LED start#define HWPF_5120_P0_LED0_MODE GPIOL_LINK_ACT_LED#define HWPF_5120_P0_LED1_MODE GPIOL_SPEED_LED#define HWPF_5120_P0_LED2_MODE GPIOL_DUPLEX_COL_LED// PORT0 LED end//******************************************************//******************************************************// PORT1 LED start#define HWPF_5120_P1_LED0_MODE GPIOL_LINK_ACT_LED#define HWPF_5120_P1_LED1_MODE GPIOL_SPEED_LED#define HWPF_5120_P1_LED2_MODE GPIOL_DUPLEX_COL_LED// PORT1 LED end//******************************************************//******************************************************// PORT2 LED start#define HWPF_5120_P2_LED0_MODE GPIOL_LINK_ACT_LED#define HWPF_5120_P2_LED1_MODE GPIOL_SPEED_LED#define HWPF_5120_P2_LED2_MODE GPIOL_DUPLEX_COL_LED// PORT2 LED end//******************************************************//******************************************************// PORT3 LED start#define HWPF_5120_P3_LED0_MODE GPIOL_LINK_ACT_LED#define HWPF_5120_P3_LED1_MODE GPIOL_SPEED_LED#define HWPF_5120_P3_LED2_MODE GPIOL_DUPLEX_COL_LED// PORT3 LED end//******************************************************//******************************************************// PORT4 LED start#define HWPF_5120_P4_LED0_MODE GPIOL_LINK_ACT_LED#define HWPF_5120_P4_LED1_MODE GPIOL_SPEED_LED#define HWPF_5120_P4_LED2_MODE GPIOL_DUPLEX_COL_LED// PORT4 LED end//******************************************************//***************************************************************************// PORT LED configuration sections end//***************************************************************************//================= Switch grouping configuration ================#define IF_BRIDGE_DISABLE 0#define IF_BRIDGE_ATTACH 0x10#define IF_BRIDGE_HOSTIF 0x20// HWPF_5120_IF_NUM MUST be a number between 0 and 6//<< HWPF_5120_IF_NUM#define HWPF_5120_IF_NUM 2//>> HWPF_5120_IF_NUM//<< HWPF_5120_IF_PORTMASK#define HWPF_5120_IF0_PORTMASK 0x06#define HWPF_5120_IF0_BRIDGE_FG (IF_BRIDGE_ATTACH | IF_BRIDGE_HOSTIF)#define HWPF_5120_IF1_PORTMASK 0x01#define HWPF_5120_IF1_BRIDGE_FG IF_BRIDGE_DISABLE#define HWPF_5120_IF2_PORTMASK 0x38#define HWPF_5120_IF2_BRIDGE_FG IF_BRIDGE_ATTACH//>> HWPF_5120_IF_PORTMASK// !!!! Do not modify the following sections !!!!// All configurable parameters are listed in the configuration secions above!!//===========================================================================// ++++++++++++++++++++++ SMEM bank0 start ++++++++++++++++++++++#if (HWPF_5120_SMEM0_BANK_SIZE <= 0x80000)#define SMEM0_BANK_SIZE ROM_SIZE_512KBYTES#elif (HWPF_5120_SMEM0_BANK_SIZE <= 0x100000)#define SMEM0_BANK_SIZE ROM_SIZE_1MBYTES#elif (HWPF_5120_SMEM0_BANK_SIZE <= 0x200000)#define SMEM0_BANK_SIZE ROM_SIZE_2MBYTES#elif (HWPF_5120_SMEM0_BANK_SIZE <= 0x400000)#define SMEM0_BANK_SIZE ROM_SIZE_4MBYTES#else#error SRAM0 which size is larger than 4M bytes is not supported!!#endif // (HWPF_5120_SMEM0_BANK_SIZE <= 0x80000)#if (HWPF_5120_SMEM0_BUS_WIDTH == 32) #define SMEM0_BUS_WIDTH SM_MEM_WIDTH_32BIT#elif (HWPF_5120_SMEM0_BUS_WIDTH == 16) #define SMEM0_BUS_WIDTH SM_MEM_WIDTH_16BIT#elif (HWPF_5120_SMEM0_BUS_WIDTH == 8) #define SMEM0_BUS_WIDTH SM_MEM_WIDTH_8BIT#else#error The value of HWPF_5120_SMEM0_BUS_WIDTH must be either 8, 16, or 32!!!!#endif // (HWPF_5120_SMEM0_BUS_WIDTH == 32)#if (HWPF_5120_SMEM0_DEV_WIDTH == 32)#define SMEM0_PB SM_PB#elif (HWPF_5120_SMEM0_DEV_WIDTH == 16)#define SMEM0_PB SM_PB#elif (HWPF_5120_SMEM0_DEV_WIDTH == 8)#define SMEM0_PB 0#else#error The value of HWPF_5120_SMEM0_DEV_WIDTH must be either 8, 16, or 32!!!!#endif // (HWPF_5120_SMEM0_DEV_WIDTH == 32)#if (HWPF_5120_SMEM0_BUS_WIDTH < HWPF_5120_SMEM0_DEV_WIDTH)#warning The data bus width of static memory bank 0 is smaller than the width of the device !!!#endif#if HWPF_5120_SMEM0_CS_POLARITY == 1#define SMEM0_CS_POLARITY SM_CS_HIGH#elif HWPF_5120_SMEM0_CS_POLARITY == 0#define SMEM0_CS_POLARITY 0#else#error The value of HWPF_5120_SMEM0_CS_POLARITY must be either 1 or 0!!!#endif // (HWPF_5120_SMEM0_CS_POLARITY == 1)#if HWPF_5120_SMEM0_PAGE_MODE == OPTION_ENABLE#define SMEM0_PM_MODE SM_PAGE_MODE#elif HWPF_5120_SMEM0_PAGE_MODE == OPTION_DISABLE#define SMEM0_PM_MODE 0#else#error The value of HWPF_5120_SMEM0_PAGE_MODE must be either OPTION_ENABLE or OPTION_DISABLE!!!#endif // (HWPF_5120_SMEM0_PAGE_MODE == 1)#if (HWPF_5120_SMEM0_CS_TO_WE_WAIT < 0) || (HWPF_5120_SMEM0_CS_TO_WE_WAIT > 15)#error HWPF_5120_SMEM0_CS_TO_WE_WAIT is out of range!!!#endif#if (HWPF_5120_SMEM0_CS_TO_OE_WAIT < 0) || (HWPF_5120_SMEM0_CS_TO_OE_WAIT > 15)#error HWPF_5120_SMEM0_CS_TO_OE_WAIT is out of range!!!#endif#if (HWPF_5120_SMEM0_READ_WAIT < 0) || (HWPF_5120_SMEM0_READ_WAIT > 31)#error HWPF_5120_SMEM0_READ_WAIT is out of range!!!#endif#if (HWPF_5120_SMEM0_WRITE_WAIT < 0) || (HWPF_5120_SMEM0_WRITE_WAIT >31)#error HWPF_5120_SMEM0_WRITE_WAIT is out of range!!!#endif#if (HWPF_5120_SMEM0_TURN_WAIT < 0) || (HWPF_5120_SMEM0_TURN_WAIT > 15)#error HWPF_5120_SMEM0_TURN_WAIT is out of range!!!#endif#define SMEM0_CFG ( SMEM0_BUS_WIDTH \ | SMEM0_CS_POLARITY \ | SMEM0_PM_MODE \ | SMEM0_PB)#define SmemBank0_Config SMEM0_CFG#define SmemBank0_WaitWen HWPF_5120_SMEM0_CS_TO_WE_WAIT#define SmemBank0_WaitOen HWPF_5120_SMEM0_CS_TO_OE_WAIT#define SmemBank0_WaitRd HWPF_5120_SMEM0_READ_WAIT#define SmemBank0_WaitPage 31#define SmemBank0_WaitWr HWPF_5120_SMEM0_WRITE_WAIT#define SmemBank0_WaitTurn HWPF_5120_SMEM0_TURN_WAIT#define HWPF_5120_SMEM0_BASE ADM5120_SMEM0_BASE#define HWPF_5120_SMEM0_SIZE HWPF_5120_SMEM0_BANK_SIZE// ++++++++++++++++++++++ SMEM bank0 end ++++++++++++++++++++++//===========================================================================//===========================================================================// ++++++++++++++++++++++ SMEM bank1 start ++++++++++++++++++++++#if (HWPF_5120_SMEM1_EN == OPTION_ENABLE)#if (HWPF_5120_SMEM1_NAND == OPTION_ENABLE) // NAND FLASH #define SMEM1_BANK_SIZE ROM_SIZE_512KBYTES#define SMEM1_BUS_WIDTH SM_MEM_WIDTH_8BIT#define SMEM1_PB SM_PB#else /* !!(HWPF_5120_SMEM1_NAND == OPTION_ENABLE) */#if (HWPF_5120_SMEM1_BANK_SIZE <= 0x80000)#define SMEM1_BANK_SIZE ROM_SIZE_512KBYTES#elif (HWPF_5120_SMEM1_BANK_SIZE <= 0x100000)#define SMEM1_BANK_SIZE ROM_SIZE_1MBYTES#elif (HWPF_5120_SMEM1_BANK_SIZE <= 0x200000)#define SMEM1_BANK_SIZE ROM_SIZE_2MBYTES#elif (HWPF_5120_SMEM1_BANK_SIZE <= 0x400000)#define SMEM1_BANK_SIZE ROM_SIZE_4MBYTES#elif (HWPF_5120_SMEM1_BANK_SIZE <= 0x800000)#define SMEM1_BANK_SIZE ROM_SIZE_8MBYTES#else#error SRAM1 which size is larger than 8M bytes is not supported!!#endif // (HWPF_5120_SMEM1_BANK_SIZE <= 0x80000)#if (HWPF_5120_SMEM1_BUS_WIDTH == 32) #define SMEM1_BUS_WIDTH SM_MEM_WIDTH_32BIT#elif (HWPF_5120_SMEM1_BUS_WIDTH == 16) #define SMEM1_BUS_WIDTH SM_MEM_WIDTH_16BIT#elif (HWPF_5120_SMEM1_BUS_WIDTH == 8) #define SMEM1_BUS_WIDTH SM_MEM_WIDTH_8BIT#else#error The value of HWPF_5120_SMEM1_BUS_WIDTH must be either 8, 16, or 32!!!!#endif // (HWPF_5120_SMEM1_BUS_WIDTH == 32)#if (HWPF_5120_SMEM1_DEV_WIDTH == 32)#define SMEM1_PB SM_PB#elif (HWPF_5120_SMEM1_DEV_WIDTH == 16)#define SMEM1_PB SM_PB#elif (HWPF_5120_SMEM1_DEV_WIDTH == 8)#define SMEM1_PB 0#else#error The value of HWPF_5120_SMEM1_DEV_WIDTH must be either 8, 16, or 32!!!!#endif // (HWPF_5120_SMEM1_DEV_WIDTH == 32)#if (HWPF_5120_SMEM1_BUS_WIDTH < HWPF_5120_SMEM1_DEV_WIDTH)#warning The data bus width of static memory bank 1 is smaller than the width of the device !!!#endif#endif /* !!(HWPF_5120_SMEM1_NAND == OPTION_ENABLE) */#if HWPF_5120_SMEM1_CS_POLARITY == 1#define SMEM1_CS_POLARITY SM_CS_HIGH#elif HWPF_5120_SMEM1_CS_POLARITY == 0#define SMEM1_CS_POLARITY 0#else#error The value of HWPF_5120_SMEM1_CS_POLARITY must be either 1 or 0!!!#endif // (HWPF_5120_SMEM1_CS_POLARITY == 1)#if HWPF_5120_SMEM1_PAGE_MODE == OPTION_ENABLE#define SMEM1_PM_MODE SM_PAGE_MODE#elif HWPF_5120_SMEM1_PAGE_MODE == OPTION_DISABLE#define SMEM1_PM_MODE 0
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