hw5120cfg.h

Boot code for ADM5120 with serial console for Edimax router.

/*****************************************************************************
;
;   (C) Unpublished Work of ADMtek Incorporated.  All Rights Reserved.
;
;       THIS WORK IS AN UNPUBLISHED WORK AND CONTAINS CONFIDENTIAL,
;       PROPRIETARY AND TRADESECRET INFORMATION OF ADMTEK INCORPORATED.
;       ACCESS TO THIS WORK IS RESTRICTED TO (I) ADMTEK EMPLOYEES WHO HAVE A
;       NEED TO KNOW TO PERFORM TASKS WITHIN THE SCOPE OF THEIR ASSIGNMENTS
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;
;------------------------------------------------------------------------------
;
;    Project : ADM5120
;    Creator : David Weng
;    File    : hw5120cfg.h
;    Abstract: 
;
;Modification History:
; 
;
;*****************************************************************************/

#ifndef __HW5120CFG_H__
#define __HW5120CFG_H__

#include <memdev.h>

#define OPTION_ENABLE						1
#define OPTION_DISABLE						0


//=================  5120 Core configuration  ================
// CPU clock options
#define _CPU_CLOCK_175M				175000000
#define _CPU_CLOCK_200M				200000000
#define _CPU_CLOCK_225M				225000000
#define _CPU_CLOCK_250M				250000000
// CPU clock options

//<< HWPF_5120_CPU_CLOCK
#define HWPF_5120_CPU_CLOCK     _CPU_CLOCK_175M
//>> HWPF_5120_CPU_CLOCK
//==============  End of 5106 Core configuration  =============


//***************************************************************************
// Memory configuration sections start
//***************************************************************************

//===========================================================================
//  Flash configuration section start
#ifdef FLASH_4M
#define BOARD_NOR_FLASH_SIZE    0x400000
#endif

#ifdef FLASH_2M
#define BOARD_NOR_FLASH_SIZE    0x200000
#endif


//******************************************************
// Size of static memory bank 0 (Unit: Byte)
#define HWPF_5120_SMEM0_BANK_SIZE					BOARD_NOR_FLASH_SIZE

// Data bus width of static memory bank 0. (legal value are 8, 16 and 32)
#define HWPF_5120_SMEM0_BUS_WIDTH					16

// Device data bus width of static memory bank 0. (legal value are 8, 16 and 32)
#define HWPF_5120_SMEM0_DEV_WIDTH					16

// Chip select polarity	[legal value are 0(low active) and 1(high active)]
#define HWPF_5120_SMEM0_CS_POLARITY					0

// Asyn page mode	[legal value are OPTION_DISABLE and OPTION_ENABLE]
#define HWPF_5120_SMEM0_PAGE_MODE					OPTION_DISABLE

// Chip select to Output enable wait state: 
//		(HWPF_5120_SMEM0_CS_TO_OE_WAIT) wait state will be inserted.
// Unit: clock, range [0-15]
#define HWPF_5120_SMEM0_CS_TO_OE_WAIT				0

// Read Wait state. (HWPF_5120_SMEM0_READ_WAIT + 1) wait state will be inserted.
// Unit: clock, range [0-31]
#define HWPF_5120_SMEM0_READ_WAIT					9

// Chip select to Write enable wait state: 
//		(HWPF_5120_SMEM0_CS_TO_WE_WAIT + 1) wait state will be inserted.
// Unit: clock, range [0-15]
#define HWPF_5120_SMEM0_CS_TO_WE_WAIT				0

// Write Wait state. (HWPF_5120_SMEM0_WRITE_WAIT + 2) wait state will be inserted.
// Unit: clock, range [0-31]
#define HWPF_5120_SMEM0_WRITE_WAIT					9

// Bus turnaround Wait state. (HWPF_5120_SMEM0_TURN_WAIT + 1) wait state will be inserted.
// Unit: clock, range [0-15]
#define HWPF_5120_SMEM0_TURN_WAIT					5

	

//******************************************************
// Size of static memory bank 1 (Unit: Byte)
// Enable or Disable bank 1
#define HWPF_5120_SMEM1_EN							OPTION_DISABLE

// static memory bank1 connected to a NAND flash
#define HWPF_5120_SMEM1_NAND						OPTION_DISABLE

// Size of static memory bank 1 (Unit: Byte)
#define HWPF_5120_SMEM1_BANK_SIZE					0x200000

// Bus width of static memory bank 1. (legal value are 8, 16 and 32)
// HWPF_5120_SMEM1_BUS_WIDTH must be 8 when HWPF_5120_SMEM1_NAND is enabled.
#define HWPF_5120_SMEM1_BUS_WIDTH					16

// Device data bus width of static memory bank 1. (legal value are 8, 16 and 32)
// HWPF_5120_SMEM1_DEV_WIDTH must be 8 when HWPF_5120_SMEM1_NAND is enabled.
#define HWPF_5120_SMEM1_DEV_WIDTH					16

// Chip select polarity	[legal value are 0(low active) and 1(high active)]
#define HWPF_5120_SMEM1_CS_POLARITY					0

// Asyn page mode	[legal value are OPTION_DISABLE and OPTION_ENABLE]
#define HWPF_5120_SMEM1_PAGE_MODE					OPTION_DISABLE

// Chip select to Output enable wait state: 
//		(HWPF_5120_SMEM1_CS_TO_OE_WAIT) wait state will be inserted.
// Unit: clock, range [0-15]
#define HWPF_5120_SMEM1_CS_TO_OE_WAIT				0

// Read Wait state. (HWPF_5120_SMEM1_READ_WAIT + 1) wait state will be inserted.
// Unit: clock, range [0-31]
#define HWPF_5120_SMEM1_READ_WAIT					9


// Chip select to Write enable wait state: 
//		(HWPF_5120_SMEM1_CS_TO_WE_WAIT + 1) wait state will be inserted.
// Unit: clock, range [0-15]
#define HWPF_5120_SMEM1_CS_TO_WE_WAIT				0

// Write Wait state. (HWPF_5120_SMEM1_WRITE_WAIT + 1) wait state will be inserted.
// Unit: clock, range [0-31]
#define HWPF_5120_SMEM1_WRITE_WAIT					9

// Bus turnaround Wait state. (HWPF_5120_SMEM1_TURN_WAIT + 1) wait state will be inserted.
// Unit: clock, range [0-15]
#define HWPF_5120_SMEM1_TURN_WAIT					1


//  Flash configuration section end
//===========================================================================


//===========================================================================
//  SDRAM configuration section start


//********************************************* SDRAM configuration of Bank 0
// RAS and CAS latency, ref: SDRAM data sheet.
// SDRAM CAS latency, legal value are 2 or 3 (clock)
// CAS latency 2 clock time could be applied to most SDRAM with clock rate below 100M Hz.
#define HWPF_5120_SDRAM0_CAS_LATENCY				2

// RAS to CAS latency must be greater than tRCD (Active to read/write delay)
// SDRAM RAS to CAS latency, legal value are 1, 2, or 3 (Clock)
#define HWPF_5120_SDRAM0_RAS_LATENCY				2

// Bus width of SDRAM bank0. legal values are 16 or 32
#define HWPF_5120_SDRAM0_BUS_WIDTH					BOARD_SDRAM0_BUS_WIDTH

// memory size of SDRAM chip in Mbits
#define HWPF_5120_SDRAM0_DEV_SIZE					BOARD_SDRAM0_DEV_SIZE

// data bus width of SDRAM chip. legal value are 8, 16 or 32
#define HWPF_5120_SDRAM0_DEV_DATA_WIDTH				BOARD_SDRAM0_DEV_DATA_WIDTH

//******************************************** SDRAM configuration of Bank 1
// RAS and CAS latency, ref: SDRAM data sheet.
// SDRAM bank 1 enable.
#define HWPF_5120_SDRAM1_EN						    BOARD_5120_SDRAM1_STATUS

// SDRAM CAS latency, legal value are 2 or 3 (clock)
// CAS latency 2 clock time could be applied to most SDRAM with clock rate below 100M Hz.
#define HWPF_5120_SDRAM1_CAS_LATENCY				2

// RAS to CAS latency must be greater than tRCD (Active to read/write delay)
// SDRAM RAS to CAS latency, legal value are 1, 2, or 3 (Clock)
#define HWPF_5120_SDRAM1_RAS_LATENCY				2

// Bus width of SDRAM bank0. legal values are 16 or 32
#define HWPF_5120_SDRAM1_BUS_WIDTH					BOARD_SDRAM1_BUS_WIDTH

// memory size of SDRAM chip in Mbits
#define HWPF_5120_SDRAM1_DEV_SIZE					BOARD_SDRAM1_DEV_SIZE

// data bus width of SDRAM chip. legal value are 8, 16 or 32
#define HWPF_5120_SDRAM1_DEV_DATA_WIDTH				BOARD_SDRAM1_DEV_DATA_WIDTH


//******************************************** SDRAM access timing parameters 
// SDRAM refresh time. (Time unit: 16 SDRAM clock)
// Assume 100M Hz clock, refresh time 15.625 us
#define HWPF_5120_SDRAM_RFTIME						85
// #define HWPF_5120_SDRAM_RFTIME						98
// DE
// I think 98 is correct but will stick with what's actually on
// the flash now to avoid another unknown variable.

// DE
// Hawking H2W54G has 2 Hynix HY57V281620HCT devices.
// Hynix spec sheet says refresh time is 64 ms.
// and SDRAM refresh freq is 100 MHz.
// None of these even come close to whatever that
// last number - 85 - is supposed to represent.

// Modify the following parameters according to the SDRAM device choosen.
// The time unit is the system clock.

// PRECHARGE command period. (HWPF_5120_SDRAM_tRP + 1) clock cycles.
// Range: [0-15]
// define HWPF_5120_SDRAM_tRP						1
#define HWPF_5120_SDRAM_tRP							1
// DE

// ACTIVE to PRECHARGE command. (HWPF_5120_SDRAM_tRAS + 1) clock cycles.
// Range [0-15]
// #define HWPF_5120_SDRAM_tRAS						4
#define HWPF_5120_SDRAM_tRAS						4
// DE

// Self-REFRESH exit time. (HWPF_5120_SDRAM_tSREX + 1) clock cycles.
// Range [0-15]
#define HWPF_5120_SDRAM_tSREX					15
// #define HWPF_5120_SDRAM_tSREX						0
// DE Hynix tSRE
//    I think 0 is correct, but went back to 15 to match real page0 value

// Last-Data-Out to ACTIVE command. (HWPF_5120_SDRAM_tAPR + 1) clock cycles.
// Range [0-15]
// #define HWPF_5120_SDRAM_tAPR						1
#define HWPF_5120_SDRAM_tAPR						1
// DE ??? No Hynix number

// Data-in to ACTIVE command. (HWPF_5120_SDRAM_tDAL + 1) clock cycles.
// Range [0-15]
#define HWPF_5120_SDRAM_tDAL						3
// #define HWPF_5120_SDRAM_tDAL						4
// DE
//    I think 4 is correct, but went back to 3 to match real page0 value

// WRITE recovery time. (HWPF_5120_SDRAM_tWR + 1) clock cycles.
// Range [0-15]
// #define HWPF_5120_SDRAM_tWR						1
#define HWPF_5120_SDRAM_tWR							1
// DE ??? No Hynix number

// ACTIVE to ACTIVE command period. (HWPF_5120_SDRAM_tRC + 1) clock cycles.
// Range[0-31]
// #define HWPF_5120_SDRAM_tRC						6
#define HWPF_5120_SDRAM_tRC							6
// DE

// AUTO REFRESH period. (HWPF_5120_SDRAM_tRFC + 1) clock cycles.
// Range[0-31]
// #define HWPF_5120_SDRAM_tRFC						6
#define HWPF_5120_SDRAM_tRFC						6
// DE

// Exit SELF-REFRESH to ACTIVE command. (HWPF_5120_SDRAM_tXSR + 1) clock cycles.
// Range[0-31]
// #define HWPF_5120_SDRAM_tXSR						7
#define HWPF_5120_SDRAM_tXSR						7
// DE Hynix No Hynix number

// ACTIVE bank a to ACTIVE bank b command. (HWPF_5120_SDRAM_tRRD + 1) clock cycles.
// Range[0-15]
// #define HWPF_5120_SDRAM_tRRD						1
#define HWPF_5120_SDRAM_tRRD						1
// DE

// Load MODE register to ACTIVE command. (HWPF_5120_SDRAM_tMRD + 1) clock cycles.
// Range[0-15]
// #define HWPF_5120_SDRAM_tMRD						1
#define HWPF_5120_SDRAM_tMRD						1
// DE


//  SDRAM configuration section end
//===========================================================================
//***************************************************************************
// Memory configuration sections end
//***************************************************************************

//***************************************************************************
// Ext I/O configuration sections start
//***************************************************************************

//******************************************************
// Ext I/O bank 0 start
// Enable or Disable bank 0
#define HWPF_5120_EXTIO0_EN							OPTION_DISABLE

// Interrupt polarity [legal value are 0(low active) and 1(high active)]
#define HWPF_5120_EXTIO0_INT_POLARITY				1

// Enable wait control
// This OPTION is ORed with HWPF_5120_EXTIO1_WAIT_EN!!
#define HWPF_5120_EXTIO0_WAIT_EN					OPTION_DISABLE

// Bus width of Ext I/o bank 0. (legal value are 8, 16 and 32)
#define HWPF_5120_EXTIO0_BUS_WIDTH					8

// Device data bus width of Ext I/o bank 0. (legal value are 8, 16 and 32)
#define HWPF_5120_EXTIO0_DEV_WIDTH					8

// Chip select polarity	[legal value are 0(low active) and 1(high active)]
#define HWPF_5120_EXTIO0_CS_POLARITY				0

// Asyn page mode	[legal value are OPTION_DISABLE and OPTION_ENABLE]
#define HWPF_5120_EXTIO0_PAGE_MODE					OPTION_DISABLE

// Chip select to Output enable wait state: 
//		(HWPF_5120_SMEM0_CS_TO_OE_WAIT) wait state will be inserted.
// Unit: clock, range [0-15]
#define HWPF_5120_EXTIO0_CS_TO_OE_WAIT				0

// Read Wait state. (HWPF_5120_EXTIO0_READ_WAIT + 1) wait state will be inserted.
// Unit: clock, range [0-31]
#define HWPF_5120_EXTIO0_READ_WAIT					3

// Chip select to Write enable wait state: 
//		(HWPF_5120_EXTIO0_CS_TO_WE_WAIT + 1) wait state will be inserted.
// Unit: clock, range [0-15]
#define HWPF_5120_EXTIO0_CS_TO_WE_WAIT				0

// Write Wait state. (HWPF_5120_EXTIO0_WRITE_WAIT + 2) wait state will be inserted.
// Unit: clock, range [0-31]
#define HWPF_5120_EXTIO0_WRITE_WAIT					3

// Bus turnaround Wait state. (HWPF_5120_EXTIO0_TURN_WAIT + 1) wait state will be inserted.
// Unit: clock, range [0-15]
#define HWPF_5120_EXTIO0_TURN_WAIT					1

// Ext I/O bank 0 end
//******************************************************

//******************************************************
// Ext I/O bank 1 start
// Enable or Disable bank 1
#define HWPF_5120_EXTIO1_EN							OPTION_DISABLE

// Interrupt polarity [legal value are 0(low active) and 1(high active)]