📄 jpeginit.asm
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;******************************************************************************
;* TMS320C6x ANSI C Codegen Version 4.10 *
;* Date/Time created: Tue Jun 01 19:58:13 2004 *
;******************************************************************************
;******************************************************************************
;* GLOBAL FILE PARAMETERS *
;* *
;* Architecture : TMS320C620x *
;* Optimization : Enabled at level 3 *
;* Optimizing for : Speed *
;* Based on options: -o3, no -ms *
;* Endian : Little *
;* Interrupt Thrshld : Disabled *
;* Memory Model : Small *
;* Calls to RTS : Near *
;* Pipelining : Enabled *
;* Speculative Load : Disabled *
;* Memory Aliases : Presume are aliases (pessimistic) *
;* Debug Info : Debug *
;* *
;******************************************************************************
.asg A15, FP
.asg B14, DP
.asg B15, SP
.global $bss
.file "jpeginit.c"
.sect ".cinit:c"
.align 8
.field (CIR - $) - 8, 32
.field _DC_MAX_QUANTED+0,32
.field 2047,32 ; _DC_MAX_QUANTED @ 0
.sect ".text"
_DC_MAX_QUANTED: .usect ".bss:c",4,4
.sym _DC_MAX_QUANTED,_DC_MAX_QUANTED, 4, 3, 32
.sect ".cinit:c"
.align 4
.field -2048,32 ; _DC_MIN_QUANTED @ 0
.sect ".text"
_DC_MIN_QUANTED: .usect ".bss:c",4,4
.sym _DC_MIN_QUANTED,_DC_MIN_QUANTED, 4, 3, 32
; d:\ti\c6000\cgtools\bin\opt6x.exe -q -O3 D:\DOCUME~1\wp\LOCALS~1\Temp\TI1248_2 D:\DOCUME~1\wp\LOCALS~1\Temp\TI1248_4 -w D:/dspbackup/jpegdsp/Debug
.sect ".text"
.global _Initimage
.sym _Initimage,_Initimage, 32, 2, 0
.func 186
;******************************************************************************
;* FUNCTION NAME: _Initimage *
;* *
;* Regs Modified : A0,A3,B0,B4,B5,B6,B7 *
;* Regs Used : A0,A3,A4,B0,B3,B4,B5,B6,B7 *
;* Local Frame Size : 0 Args + 0 Auto + 0 Save = 0 byte *
;******************************************************************************
_Initimage:
;** --------------------------------------------------------------------------*
.line 2
.sym _lpInBuff,4, 20, 17, 32
.sym _lpInBuff,0, 20, 4, 32
MV .D1 A4,A0
|| MVK .S2 0xffffffff,B5
.line 4
MV .S1X B5,A3
|| MV .L2X A0,B4
|| MVC .S2 CSR,B6
AND .S2 -2,B6,B7
|| STW .D1T1 A3,*+A0(12) ; (P) ^ |191|
|| STW .D2T2 B5,*+B4(28) ; (P) ^ |191|
MVC .S2 B7,CSR ; interrupts off
|| STW .D2T2 B5,*+B4(24) ; (P) ^ |191|
|| STW .D1T1 A3,*+A0(8) ; (P) ^ |191|
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 189
;* Loop opening brace source line : 190
;* Loop closing brace source line : 191
;* Known Minimum Trip Count : 640
;* Known Maximum Trip Count : 640
;* Known Max Trip Count Factor : 640
;* Loop Carried Dependency Bound(^) : 1
;* Unpartitioned Resource Bound : 4
;* Partitioned Resource Bound(*) : 4
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 2 1
;* .D units 4* 4*
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 4* 4*
;* Long read paths 4* 4*
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 0 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1 1
;* Bound(.L .S .D .LS .LSD) 2 2
;*
;* Searching for software pipeline schedule at ...
;* ii = 4 Schedule found with 2 iterations in parallel
;* done
;*
;* Collapsed epilog stages : 0
;* Prolog not removed
;* Collapsed prolog stages : 0
;*
;* Minimum required memory pad : 0 bytes
;*
;* Minimum safe trip count : 2
;*----------------------------------------------------------------------------*
L1: ; PIPED LOOP PROLOG
MVK .S2 0x280,B7 ; |189|
|| STW .D1T1 A3,*+A0(4) ; (P) ^ |191|
|| B .S1 L2 ; (P) |191|
|| STW .D2T2 B5,*+B4(20) ; (P) ^ |191|
SUB .L2 B7,2,B0
|| STW .D1T1 A3,*A0 ; (P) ^ |191|
|| STW .D2T2 B5,*+B4(16) ; (P) ^ |191|
|| ADDK .S2 2560,B4 ; (P) ^ |191|
|| ADDK .S1 2560,A0 ; (P) ^ |191|
;** --------------------------------------------------------------------------*
L2: ; PIPED LOOP KERNEL
STW .D1T1 A3,*+A0(12) ; @ ^ |191|
|| STW .D2T2 B5,*+B4(28) ; @ ^ |191|
STW .D1T1 A3,*+A0(8) ; @ ^ |191|
|| STW .D2T2 B5,*+B4(24) ; @ ^ |191|
|| [ B0] SUB .S2 B0,1,B0 ; @|191|
STW .D1T1 A3,*+A0(4) ; @ ^ |191|
|| STW .D2T2 B5,*+B4(20) ; @ ^ |191|
|| [ B0] B .S1 L2 ; @|191|
STW .D1T1 A3,*A0 ; @ ^ |191|
|| ADDK .S1 2560,A0 ; @ ^ |191|
|| STW .D2T2 B5,*+B4(16) ; @ ^ |191|
|| ADDK .S2 2560,B4 ; @ ^ |191|
;** --------------------------------------------------------------------------*
L3: ; PIPED LOOP EPILOG
MVC .S2 B6,CSR ; interrupts on
.line 7
B .S2 B3 ; |192|
NOP 5
; BRANCH OCCURS ; |192|
.endfunc 192,000000000h,0
.sect ".text"
.global _ComputeVLI
.sym _ComputeVLI,_ComputeVLI, 44, 2, 0
.func 106
;******************************************************************************
;* FUNCTION NAME: _ComputeVLI *
;* *
;* Regs Modified : A0,A1,A3,A4,A5,B0,B1,B4,B5 *
;* Regs Used : A0,A1,A3,A4,A5,B0,B1,B3,B4,B5 *
;* Local Frame Size : 0 Args + 0 Auto + 0 Save = 0 byte *
;******************************************************************************
_ComputeVLI:
;** --------------------------------------------------------------------------*
.line 2
.sym _val,4, 3, 17, 16
.sym _val,4, 3, 4, 16
.line 6
ABS .L1 A4,A0 ; |111|
EXT .S1 A0,16,16,A0 ; |111|
CMPEQ .L1 A0,1,A1 ; |111|
.line 9
[ A1] B .S1 L6 ; |114|
[ A1] MVK .S1 0x1,A3 ; |114|
NOP 4
; BRANCH OCCURS ; |114|
;** --------------------------------------------------------------------------*
.line 10
CMPLT .L1 A0,2,A4 ; |115|
XOR .S1 1,A4,A4 ; |115|
|| CMPLT .L2X A0,4,B4 ; |115|
AND .S2X B4,A4,B0 ; |115|
.line 13
[ B0] B .S1 L6 ; |118|
[ B0] MVK .S1 0x2,A3 ; |118|
NOP 4
; BRANCH OCCURS ; |118|
;** --------------------------------------------------------------------------*
.line 14
CMPLT .L1 A0,4,A4 ; |119|
XOR .S1 1,A4,A4 ; |119|
|| CMPLT .L2X A0,8,B4 ; |119|
AND .S2X B4,A4,B0 ; |119|
.line 17
[ B0] B .S1 L6 ; |122|
[ B0] MVK .S1 0x3,A3 ; |122|
NOP 4
; BRANCH OCCURS ; |122|
;** --------------------------------------------------------------------------*
.line 18
MVK .S1 16,A4 ; |123|
|| CMPLT .L1 A0,8,A5 ; |123|
CMPLT .L1 A0,A4,A5 ; |123|
|| XOR .S1 1,A5,A4 ; |123|
AND .S1 A5,A4,A1 ; |123|
.line 21
[ A1] B .S1 L6 ; |126|
[ A1] MVK .S1 0x4,A3 ; |126|
NOP 4
; BRANCH OCCURS ; |126|
;** --------------------------------------------------------------------------*
.line 22
MVK .S1 16,A4 ; |127|
CMPLT .L1 A0,A4,A4 ; |127|
|| MVK .S2 32,B4 ; |127|
XOR .S1 1,A4,A4 ; |127|
|| CMPLT .L2X A0,B4,B4 ; |127|
AND .S2X B4,A4,B0 ; |127|
.line 25
[ B0] B .S1 L6 ; |130|
[ B0] MVK .S1 0x5,A3 ; |130|
NOP 4
; BRANCH OCCURS ; |130|
;** --------------------------------------------------------------------------*
.line 26
MVK .S1 32,A4 ; |131|
CMPLT .L1 A0,A4,A4 ; |131|
|| MVK .S2 64,B4 ; |131|
XOR .S1 1,A4,A4 ; |131|
|| CMPLT .L2X A0,B4,B4 ; |131|
AND .S2X B4,A4,B0 ; |131|
.line 29
[ B0] B .S1 L6 ; |134|
[ B0] MVK .S1 0x6,A3 ; |134|
NOP 4
; BRANCH OCCURS ; |134|
;** --------------------------------------------------------------------------*
.line 30
MVK .S1 64,A4 ; |135|
CMPLT .L1 A0,A4,A4 ; |135|
|| MVK .S2 128,B4 ; |135|
XOR .S1 1,A4,A4 ; |135|
|| CMPLT .L2X A0,B4,B4 ; |135|
AND .S2X B4,A4,B0 ; |135|
.line 33
[ B0] B .S1 L6 ; |138|
[ B0] MVK .S1 0x7,A3 ; |138|
NOP 4
; BRANCH OCCURS ; |138|
;** --------------------------------------------------------------------------*
.line 34
MVK .S1 128,A4 ; |139|
CMPLT .L1 A0,A4,A4 ; |139|
|| MVK .S2 256,B4 ; |139|
XOR .S1 1,A4,A4 ; |139|
|| CMPLT .L2X A0,B4,B4 ; |139|
AND .S2X B4,A4,B0 ; |139|
.line 37
[ B0] B .S1 L6 ; |142|
[ B0] MVK .S1 0x8,A3 ; |142|
NOP 4
; BRANCH OCCURS ; |142|
;** --------------------------------------------------------------------------*
.line 38
MVK .S1 256,A4 ; |143|
CMPLT .L1 A0,A4,A4 ; |143|
|| MVK .S2 512,B4 ; |143|
XOR .S1 1,A4,A4 ; |143|
|| CMPLT .L2X A0,B4,B4 ; |143|
AND .S2X B4,A4,B0 ; |143|
.line 41
[ B0] B .S1 L6 ; |146|
[ B0] MVK .S1 0x9,A3 ; |146|
NOP 4
; BRANCH OCCURS ; |146|
;** --------------------------------------------------------------------------*
.line 42
MVK .S1 512,A3 ; |147|
CMPLT .L1 A0,A3,A3 ; |147|
|| MVK .S2 1024,B4 ; |147|
XOR .L1 1,A3,A3 ; |147|
|| CMPLT .L2X A0,B4,B4 ; |147|
|| MVK .S1 1024,A4 ; |147|
CMPLT .L1 A0,A4,A3 ; |147|
|| AND .S2X B4,A3,B0 ; |147|
XOR .L2 1,B0,B4 ; |147|
|| XOR .S1 1,A3,A3 ; |147|
|| MVK .S2 2048,B5 ; |147|
AND .S1X A3,B4,A0 ; |147|
|| CMPLT .L2X A0,B5,B4 ; |147|
AND .S1X B4,A0,A1 ; |147|
[ A1] B .S1 L4 ; |147|
XOR .S2 1,B0,B1 ; |147|
NOP 4
; BRANCH OCCURS ; |147|
;** --------------------------------------------------------------------------*
.line 46
[ B0] B .S1 L5 ; |151|
ZERO .D1 A3
NOP 4
; BRANCH OCCURS ; |151|
;** --------------------------------------------------------------------------*
B .S1 L6
NOP 5
; BRANCH OCCURS
;** --------------------------------------------------------------------------*
L4:
.line 48
[ B1] B .S1 L6
MVK .S1 0xb,A3
NOP 4
; BRANCH OCCURS
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