📄 seg7_1a.fit.rpt
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; count[1] ; 14 ;
; count[0] ; 14 ;
; num[2] ; 7 ;
; num[0] ; 6 ;
; num[1] ; 6 ;
; n2[0] ; 2 ;
; n2[2] ; 2 ;
; n1[1] ; 2 ;
; n3[0] ; 2 ;
; n2[1] ; 2 ;
; n3[2] ; 2 ;
; n4[2] ; 2 ;
; n3[1] ; 2 ;
; n4[0] ; 2 ;
; n5[0] ; 2 ;
; n5[2] ; 2 ;
; n4[1] ; 2 ;
; n5[1] ; 2 ;
; n0[0] ; 2 ;
; n0[2] ; 2 ;
; n1[0] ; 2 ;
; n1[2] ; 2 ;
; n0[1] ; 2 ;
; Mux~1211 ; 1 ;
; Mux~1208 ; 1 ;
; Mux~1205 ; 1 ;
; seg7_1a:u1|i[3]~105 ; 1 ;
; seg7_1a:u1|i[1]~99 ; 1 ;
; seg7_1a:u1|i[4]~96 ; 1 ;
; seg7_1a:u1|i[5]~93 ; 1 ;
; seg7_1a:u1|i[3]~88 ; 1 ;
; seg7_1a:u1|i[0]~84 ; 1 ;
; seg7_1a:u1|i[2]~82 ; 1 ;
; cat[4]~reg0 ; 1 ;
; cat[5]~reg0 ; 1 ;
; cat[2]~reg0 ; 1 ;
; cat[3]~reg0 ; 1 ;
; cat[0]~reg0 ; 1 ;
; cat[1]~reg0 ; 1 ;
+---------------------+-----------+
+------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+-------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 39 / 288 ( 13 % ) ;
; PIAs ; 43 / 288 ( 14 % ) ;
+----------------------------+-------------------+
+----------------------------------------------------------------------------+
; LAB External Interconnect ;
+----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 5.38) ; Number of LABs (Total = 5) ;
+----------------------------------------------+-----------------------------+
; 0 - 1 ; 3 ;
; 2 - 3 ; 2 ;
; 4 - 5 ; 1 ;
; 6 - 7 ; 0 ;
; 8 - 9 ; 0 ;
; 10 - 11 ; 0 ;
; 12 - 13 ; 1 ;
; 14 - 15 ; 0 ;
; 16 - 17 ; 0 ;
; 18 - 19 ; 1 ;
+----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 5.38) ; Number of LABs (Total = 5) ;
+----------------------------------------+-----------------------------+
; 0 ; 3 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 2 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 2 ;
+----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 3 ;
+--------------------------+------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+-------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+-------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC8 ; num[2], num[0], num[1] ; lcd[6] ;
; A ; LC5 ; num[2], num[0], num[1] ; lcd[4] ;
; A ; LC6 ; num[0], num[1], num[2] ; lcd[5] ;
; A ; LC3 ; num[0], num[1], num[2] ; lcd[3] ;
; B ; LC27 ; num[2], num[0], num[1] ; lcd[1] ;
; B ; LC25 ; num[2], num[1] ; lcd[0] ;
; B ; LC29 ; num[2], num[0] ; lcd[2] ;
; C ; LC46 ; clk, n0[0], btn2, count1[2], count1[1], count1[0] ; n4[0], num[0] ;
; C ; LC47 ; clk, n5[0], btn2, count1[2], count1[1], count1[0] ; n3[0], num[0] ;
; C ; LC48 ; clk, n4[1], btn2, count1[2], count1[1], count1[0] ; n2[1], num[1] ;
; C ; LC41 ; clk, n3[1], btn2, count1[2], count1[1], count1[0] ; n1[1], num[1] ;
; C ; LC40 ; clk, n4[0], btn2, count1[2], count1[1], count1[0] ; n2[0], Mux~1211 ;
; C ; LC38 ; clk, n2[1], btn2, count1[2], count1[1], count1[0] ; n0[1], Mux~1208 ;
; C ; LC39 ; clk, n3[0], btn2, count1[2], count1[1], count1[0] ; n1[0], Mux~1211 ;
; C ; LC36 ; clk, Mux~1208, n3[1], count[2], count[1], count[0], n2[1], n5[1], n4[1], btn2 ; seg7_1a:u1|i[0]~84, seg7_1a:u1|i[3]~88, seg7_1a:u1|i[5]~93, seg7_1a:u1|i[4]~96, seg7_1a:u1|i[1]~99, seg7_1a:u1|i[3]~105 ;
; C ; LC34 ; clk, Mux~1211, n0[0], count[2], count[1], count[0], n1[0], n5[0], n4[0], btn2 ; seg7_1a:u1|i[2]~82, seg7_1a:u1|i[3]~88, seg7_1a:u1|i[5]~93, seg7_1a:u1|i[4]~96, seg7_1a:u1|i[1]~99, seg7_1a:u1|i[3]~105 ;
; C ; LC35 ; n1[1], count[2], count[1], count[0], n0[1] ; num[1] ;
; C ; LC33 ; n2[0], count[2], count[1], count[0], n3[0] ; num[0] ;
; C ; LC45 ; clk, n5[1], btn2, count1[2], count1[1], count1[0] ; n3[1], num[1] ;
; C ; LC44 ; clk, n0[1], btn2, count1[2], count1[1], count1[0] ; n4[1], num[1] ;
; C ; LC43 ; clk, n1[0], btn2, count1[2], count1[1], count1[0] ; n5[0], num[0] ;
; C ; LC37 ; clk, count[2], count[0], count[1], btn2 ; count[1], cat[1]~reg0, cat[0]~reg0, count[2], cat[3]~reg0, cat[2]~reg0, cat[5]~reg0, cat[4]~reg0, num[2], num[1], num[0], Mux~1205, Mux~1208, Mux~1211 ;
; C ; LC42 ; clk, n2[0], btn2, count1[2], count1[1], count1[0] ; n0[0], num[0] ;
; D ; LC54 ; n2[2], count[2], count[1], count[0], n3[2] ; num[2] ;
; D ; LC50 ; clk, count1[2], count1[0], count1[1], btn2 ; count1[1], count1[2], n0[1], n1[2], n1[0], n0[2], n0[0], n5[1], n4[1], n5[2], n5[0], n4[0], n3[1], n4[2], n3[2], n2[1], n3[0], n1[1], n2[2], n2[0] ;
; D ; LC52 ; clk, count[2], count[1], count[0], btn2 ; count[1], cat[1]~reg0, cat[0]~reg0, count[2], cat[3]~reg0, cat[2]~reg0, cat[5]~reg0, cat[4]~reg0, num[2], num[1], num[0], Mux~1205, Mux~1208, Mux~1211 ;
; D ; LC51 ; clk, count[0], count[2], count[1], btn2 ; cat[1] ;
; D ; LC49 ; clk, count[0], count[2], count[1], btn2 ; cat[0] ;
; D ; LC61 ; clk, n2[2], btn2, count1[2], count1[1], count1[0] ; n0[2], num[2] ;
; D ; LC56 ; clk, count[0], count[2], count[1], btn2 ; cat[3] ;
; D ; LC55 ; clk, Mux~1205, n0[2], count[2], count[1], count[0], n1[2], n5[2], n4[2], btn2 ; seg7_1a:u1|i[2]~82, seg7_1a:u1|i[0]~84, seg7_1a:u1|i[3]~88, seg7_1a:u1|i[5]~93, seg7_1a:u1|i[4]~96, seg7_1a:u1|i[1]~99, seg7_1a:u1|i[3]~105 ;
; D ; LC53 ; clk, count[2], count[0], count[1], btn2 ; cat[2] ;
; D ; LC58 ; clk, n3[2], btn2, count1[2], count1[1], count1[0] ; n1[2], Mux~1205 ;
; D ; LC62 ; clk, n1[2], btn2, count1[2], count1[1], count1[0] ; n5[2], num[2] ;
; D ; LC60 ; clk, n4[2], btn2, count1[2], count1[1], count1[0] ; n2[2], Mux~1205 ;
; D ; LC64 ; clk, n5[2], btn2, count1[2], count1[1], count1[0] ; n3[2], num[2] ;
; D ; LC59 ; clk, count[0], count[2], count[1], btn2 ; cat[5] ;
; D ; LC57 ; clk, count[0], count[2], count[1], btn2 ; cat[4] ;
; D ; LC63 ; clk, n0[2], btn2, count1[2], count1[1], count1[0] ; n4[2], num[2] ;
; E ; LC68 ; clk, n1[1], btn2, count1[2], count1[1], count1[0] ; n5[1], Mux~1208 ;
; E ; LC66 ; clk, count1[1], count1[0], count1[2], btn2 ; count1[1], count1[2], n0[1], n1[2], n1[0], n0[2], n0[0], n5[1], n4[1], n5[2], n5[0], n4[0], n3[1], n4[2], n3[2], n2[1], n3[0], n1[1], n2[2], n2[0] ;
; E ; LC65 ; clk, btn2 ; count1[1], count1[2], n0[1], n1[2], n1[0], n0[2], n0[0], n5[1], n4[1], n5[2], n5[0], n4[0], n3[1], n4[2], n3[2], n2[1], n3[0], n1[1], n2[2], n2[0] ;
; E ; LC67 ; clk, btn2 ; count[1], cat[1]~reg0, cat[0]~reg0, count[2], cat[3]~reg0, cat[2]~reg0, cat[5]~reg0, cat[4]~reg0, num[2], num[1], num[0], Mux~1205, Mux~1208, Mux~1211 ;
+-----+------------+-------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Sat Apr 29 23:45:26 2006
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off main -c seg7_1a
Info: Selected device EPM7128SLC84-15 for design seg7_1a
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Apr 29 23:45:27 2006
Info: Elapsed time: 00:00:00
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