seg7_1a.map.qmsg

数码管扫描显示控制器,同时显示0、1、2、3、4、5这6个不同的数字图形到6个数码管上。复位时所有数码管全灭。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 29 23:45:22 2006 " "Info: Processing started: Sat Apr 29 23:45:22 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off main -c seg7_1a " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off main -c seg7_1a" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg7_1a.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file seg7_1a.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seg7_1a-seg7_1a_arch " "Info: Found design unit 1: seg7_1a-seg7_1a_arch" {  } { { "G:/study/experience/4k/seg7_1a.vhd" "seg7_1a-seg7_1a_arch" "" { Text "G:/study/experience/4k/seg7_1a.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 seg7_1a " "Info: Found entity 1: seg7_1a" {  } { { "G:/study/experience/4k/seg7_1a.vhd" "seg7_1a" "" { Text "G:/study/experience/4k/seg7_1a.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "main.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file main.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 main-arch_main " "Info: Found design unit 1: main-arch_main" {  } { { "G:/study/experience/4k/main.vhd" "main-arch_main" "" { Text "G:/study/experience/4k/main.vhd" 14 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 main " "Info: Found entity 1: main" {  } { { "G:/study/experience/4k/main.vhd" "main" "" { Text "G:/study/experience/4k/main.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin clk to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "58 " "Info: Implemented 58 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "43 " "Info: Implemented 43 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 29 23:45:24 2006 " "Info: Processing ended: Sat Apr 29 23:45:24 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}