seg7_1a.tan.qmsg

数码管扫描显示控制器,同时显示0、1、2、3、4、5这6个不同的数字图形到6个数码管上。复位时所有数码管全灭。

{ "Info" "ITDB_TSU_RESULT" "count1\[0\] btn2 clk 11.000 ns register " "Info: tsu for register count1\[0\] (data pin = btn2, clock pin = clk) is 11.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns btn2 1 PIN PIN_1 33 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 33; PIN Node = 'btn2'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "" { btn2 } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns count1\[0\] 2 REG LC65 23 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC65; Fanout = 23; REG Node = 'count1\[0\]'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "7.000 ns" { btn2 count1[0] } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" {  } {  } 0}  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "10.000 ns" { btn2 count1[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns count1\[0\] 2 REG LC65 23 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC65; Fanout = 23; REG Node = 'count1\[0\]'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "0.000 ns" { clk count1[0] } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "3.000 ns" { clk count1[0] } "NODE_NAME" } } }  } 0}  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "10.000 ns" { btn2 count1[0] } "NODE_NAME" } } } { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "3.000 ns" { clk count1[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk lcd\[6\] num\[2\] 17.000 ns register " "Info: tco from clock clk to destination pin lcd\[6\] through register num\[2\] is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns num\[2\] 2 REG LC55 9 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC55; Fanout = 9; REG Node = 'num\[2\]'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "0.000 ns" { clk num[2] } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "3.000 ns" { clk num[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns num\[2\] 1 REG LC55 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC55; Fanout = 9; REG Node = 'num\[2\]'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "" { num[2] } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns seg7_1a:u1\|i\[3\]~105 2 COMB LC8 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC8; Fanout = 1; COMB Node = 'seg7_1a:u1\|i\[3\]~105'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "9.000 ns" { num[2] seg7_1a:u1|i[3]~105 } "NODE_NAME" } } } { "g:/study/experience/4宿/seg7_1a.vhd" "" "" { Text "g:/study/experience/4宿/seg7_1a.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns lcd\[6\] 3 PIN PIN_9 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_9; Fanout = 0; PIN Node = 'lcd\[6\]'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "4.000 ns" { seg7_1a:u1|i[3]~105 lcd[6] } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 84.62 % " "Info: Total cell delay = 11.000 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.38 % " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" {  } {  } 0}  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "13.000 ns" { num[2] seg7_1a:u1|i[3]~105 lcd[6] } "NODE_NAME" } } }  } 0}  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "3.000 ns" { clk num[2] } "NODE_NAME" } } } { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "13.000 ns" { num[2] seg7_1a:u1|i[3]~105 lcd[6] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "count1\[0\] btn2 clk -3.000 ns register " "Info: th for register count1\[0\] (data pin = btn2, clock pin = clk) is -3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns count1\[0\] 2 REG LC65 23 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC65; Fanout = 23; REG Node = 'count1\[0\]'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "0.000 ns" { clk count1[0] } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "3.000 ns" { clk count1[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns btn2 1 PIN PIN_1 33 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 33; PIN Node = 'btn2'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "" { btn2 } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns count1\[0\] 2 REG LC65 23 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC65; Fanout = 23; REG Node = 'count1\[0\]'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "7.000 ns" { btn2 count1[0] } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" {  } {  } 0}  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "10.000 ns" { btn2 count1[0] } "NODE_NAME" } } }  } 0}  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "3.000 ns" { clk count1[0] } "NODE_NAME" } } } { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "10.000 ns" { btn2 count1[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk cat\[1\] cat\[1\]~reg0 8.000 ns register " "Info: Minimum tco from clock clk to destination pin cat\[1\] through register cat\[1\]~reg0 is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns cat\[1\]~reg0 2 REG LC51 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC51; Fanout = 1; REG Node = 'cat\[1\]~reg0'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "0.000 ns" { clk cat[1]~reg0 } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "3.000 ns" { clk cat[1]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cat\[1\]~reg0 1 REG LC51 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC51; Fanout = 1; REG Node = 'cat\[1\]~reg0'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "" { cat[1]~reg0 } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns cat\[1\] 2 PIN PIN_40 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'cat\[1\]'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "4.000 ns" { cat[1]~reg0 cat[1] } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "4.000 ns" { cat[1]~reg0 cat[1] } "NODE_NAME" } } }  } 0}  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "3.000 ns" { clk cat[1]~reg0 } "NODE_NAME" } } } { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "4.000 ns" { cat[1]~reg0 cat[1] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Apr 29 23:45:31 2006 " "Info: Processing ended: Sat Apr 29 23:45:31 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}