seg7_1a.tan.qmsg

数码管扫描显示控制器,同时显示0、1、2、3、4、5这6个不同的数字图形到6个数码管上。复位时所有数码管全灭。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 29 23:45:30 2006 " "Info: Processing started: Sat Apr 29 23:45:30 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off main -c seg7_1a " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off main -c seg7_1a" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 7 -1 0 } } { "e:/install/quartus4.1/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/install/quartus4.1/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[0\] register num\[0\] 71.43 MHz 14.0 ns Internal " "Info: Clock clk has Internal fmax of 71.43 MHz between source register count\[0\] and destination register num\[0\] (period= 14.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register register " "Info: + Longest register to register delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[0\] 1 REG LC67 29 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC67; Fanout = 29; REG Node = 'count\[0\]'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "" { count[0] } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns Mux~1211 2 COMB LC33 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC33; Fanout = 1; COMB Node = 'Mux~1211'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "8.000 ns" { count[0] Mux~1211 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns num\[0\] 3 REG LC34 7 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC34; Fanout = 7; REG Node = 'num\[0\]'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "1.000 ns" { Mux~1211 num[0] } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns 77.78 % " "Info: Total cell delay = 7.000 ns ( 77.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 22.22 % " "Info: Total interconnect delay = 2.000 ns ( 22.22 % )" {  } {  } 0}  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "9.000 ns" { count[0] Mux~1211 num[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns num\[0\] 2 REG LC34 7 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC34; Fanout = 7; REG Node = 'num\[0\]'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "0.000 ns" { clk num[0] } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "3.000 ns" { clk num[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 33 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns count\[0\] 2 REG LC67 29 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC67; Fanout = 29; REG Node = 'count\[0\]'" {  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "0.000 ns" { clk count[0] } "NODE_NAME" } } } { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "3.000 ns" { clk count[0] } "NODE_NAME" } } }  } 0}  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "3.000 ns" { clk num[0] } "NODE_NAME" } } } { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "3.000 ns" { clk count[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "G:/study/experience/4k/main.vhd" "" "" { Text "G:/study/experience/4k/main.vhd" 38 -1 0 } }  } 0}  } { { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "9.000 ns" { count[0] Mux~1211 num[0] } "NODE_NAME" } } } { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "3.000 ns" { clk num[0] } "NODE_NAME" } } } { "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" "" "" { Report "G:/study/experience/4k/db/seg7_1a_cmp.qrpt" Compiler "seg7_1a" "UNKNOWN" "V1" "G:/study/experience/4k/db/main.quartus_db" { Floorplan "" "" "3.000 ns" { clk count[0] } "NODE_NAME" } } }  } 0}