seg7_1b.map.qmsg

来自「数码管扫描显示控制器,同时显示0、1、2、3、4、5这6个不同的数字图形到6个数」· QMSG 代码 · 共 9 行

QMSG
9
字号
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Apr 29 18:18:59 2006 " "Info: Processing started: Sat Apr 29 18:18:59 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off mainb -c seg7_1b " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off mainb -c seg7_1b" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg7_1b.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file seg7_1b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seg7_1b-seg7_1_arch " "Info: Found design unit 1: seg7_1b-seg7_1_arch" {  } { { "g:/study/experience/4宿/seg7_1b.vhd" "seg7_1b-seg7_1_arch" "" { Text "g:/study/experience/4宿/seg7_1b.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 seg7_1b " "Info: Found entity 1: seg7_1b" {  } { { "g:/study/experience/4宿/seg7_1b.vhd" "seg7_1b" "" { Text "g:/study/experience/4宿/seg7_1b.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "seg7_1b mainb.vhd(69) " "Error: VHDL error at mainb.vhd(69): object seg7_1b is used but not declared" {  } { { "g:/study/experience/4宿/mainb.vhd" "" "" { Text "g:/study/experience/4宿/mainb.vhd" 69 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_UNIT_INGONRED_ERR" "arch_mainb mainb.vhd(14) " "Error: Ignored construct arch_mainb at mainb.vhd(14) because of previous errors" {  } { { "g:/study/experience/4宿/mainb.vhd" "" "" { Text "g:/study/experience/4宿/mainb.vhd" 14 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mainb.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file mainb.vhd" {  } {  } 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Sat Apr 29 18:19:01 2006 " "Error: Processing ended: Sat Apr 29 18:19:01 2006" {  } {  } 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}

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