cnt6.tan.qmsg

数码管扫描显示控制器,同时显示0、1、2、3、4、5这6个不同的数字图形到6个数码管上。复位时所有数码管全灭。

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "g:/study/experience/4宿/main1.vhd" "" "" { Text "g:/study/experience/4宿/main1.vhd" 7 -1 0 } } { "e:/install/quartus4.1/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "e:/install/quartus4.1/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt6:u1\|count\[0\] register cnt6:u1\|count\[1\] 76.92 MHz 13.0 ns Internal " "Info: Clock clk has Internal fmax of 76.92 MHz between source register cnt6:u1\|count\[0\] and destination register cnt6:u1\|count\[1\] (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt6:u1\|count\[0\] 1 REG LC37 32 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC37; Fanout = 32; REG Node = 'cnt6:u1\|count\[0\]'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "" { cnt6:u1|count[0] } "NODE_NAME" } } } { "g:/study/experience/4宿/cnt6.vhd" "" "" { Text "g:/study/experience/4宿/cnt6.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns cnt6:u1\|count\[1\] 2 REG LC38 40 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC38; Fanout = 40; REG Node = 'cnt6:u1\|count\[1\]'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "8.000 ns" { cnt6:u1|count[0] cnt6:u1|count[1] } "NODE_NAME" } } } { "g:/study/experience/4宿/cnt6.vhd" "" "" { Text "g:/study/experience/4宿/cnt6.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "8.000 ns" { cnt6:u1|count[0] cnt6:u1|count[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "g:/study/experience/4宿/main1.vhd" "" "" { Text "g:/study/experience/4宿/main1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns cnt6:u1\|count\[1\] 2 REG LC38 40 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC38; Fanout = 40; REG Node = 'cnt6:u1\|count\[1\]'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "0.000 ns" { clk cnt6:u1|count[1] } "NODE_NAME" } } } { "g:/study/experience/4宿/cnt6.vhd" "" "" { Text "g:/study/experience/4宿/cnt6.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "3.000 ns" { clk cnt6:u1|count[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "g:/study/experience/4宿/main1.vhd" "" "" { Text "g:/study/experience/4宿/main1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns cnt6:u1\|count\[0\] 2 REG LC37 32 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC37; Fanout = 32; REG Node = 'cnt6:u1\|count\[0\]'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "0.000 ns" { clk cnt6:u1|count[0] } "NODE_NAME" } } } { "g:/study/experience/4宿/cnt6.vhd" "" "" { Text "g:/study/experience/4宿/cnt6.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "3.000 ns" { clk cnt6:u1|count[0] } "NODE_NAME" } } }  } 0}  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "3.000 ns" { clk cnt6:u1|count[1] } "NODE_NAME" } } } { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "3.000 ns" { clk cnt6:u1|count[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "g:/study/experience/4宿/cnt6.vhd" "" "" { Text "g:/study/experience/4宿/cnt6.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "g:/study/experience/4宿/cnt6.vhd" "" "" { Text "g:/study/experience/4宿/cnt6.vhd" 19 -1 0 } }  } 0}  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "8.000 ns" { cnt6:u1|count[0] cnt6:u1|count[1] } "NODE_NAME" } } } { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "3.000 ns" { clk cnt6:u1|count[1] } "NODE_NAME" } } } { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "3.000 ns" { clk cnt6:u1|count[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk cat\[1\] cnt6:u1\|count\[0\] 27.000 ns register " "Info: tco from clock clk to destination pin cat\[1\] through register cnt6:u1\|count\[0\] is 27.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "g:/study/experience/4宿/main1.vhd" "" "" { Text "g:/study/experience/4宿/main1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns cnt6:u1\|count\[0\] 2 REG LC37 32 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC37; Fanout = 32; REG Node = 'cnt6:u1\|count\[0\]'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "0.000 ns" { clk cnt6:u1|count[0] } "NODE_NAME" } } } { "g:/study/experience/4宿/cnt6.vhd" "" "" { Text "g:/study/experience/4宿/cnt6.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "3.000 ns" { clk cnt6:u1|count[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "g:/study/experience/4宿/cnt6.vhd" "" "" { Text "g:/study/experience/4宿/cnt6.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "23.000 ns + Longest register pin " "Info: + Longest register to pin delay is 23.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt6:u1\|count\[0\] 1 REG LC37 32 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC37; Fanout = 32; REG Node = 'cnt6:u1\|count\[0\]'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "" { cnt6:u1|count[0] } "NODE_NAME" } } } { "g:/study/experience/4宿/cnt6.vhd" "" "" { Text "g:/study/experience/4宿/cnt6.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns seg7_1:u2\|cat0\[1\]~102 2 COMB LC62 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC62; Fanout = 1; COMB Node = 'seg7_1:u2\|cat0\[1\]~102'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "8.000 ns" { cnt6:u1|count[0] seg7_1:u2|cat0[1]~102 } "NODE_NAME" } } } { "g:/study/experience/4宿/seg7_1.vhd" "" "" { Text "g:/study/experience/4宿/seg7_1.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 10.000 ns seg7_1:u2\|cat0\[1\]~66 3 COMB LC63 4 " "Info: 3: + IC(0.000 ns) + CELL(2.000 ns) = 10.000 ns; Loc. = LC63; Fanout = 4; COMB Node = 'seg7_1:u2\|cat0\[1\]~66'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "2.000 ns" { seg7_1:u2|cat0[1]~102 seg7_1:u2|cat0[1]~66 } "NODE_NAME" } } } { "g:/study/experience/4宿/seg7_1.vhd" "" "" { Text "g:/study/experience/4宿/seg7_1.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 19.000 ns seg7_1:u2\|cat0\[1\]~109 4 COMB LC57 1 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC57; Fanout = 1; COMB Node = 'seg7_1:u2\|cat0\[1\]~109'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "9.000 ns" { seg7_1:u2|cat0[1]~66 seg7_1:u2|cat0[1]~109 } "NODE_NAME" } } } { "g:/study/experience/4宿/seg7_1.vhd" "" "" { Text "g:/study/experience/4宿/seg7_1.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 23.000 ns cat\[1\] 5 PIN PIN_36 0 " "Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 23.000 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'cat\[1\]'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "4.000 ns" { seg7_1:u2|cat0[1]~109 cat[1] } "NODE_NAME" } } } { "g:/study/experience/4宿/main1.vhd" "" "" { Text "g:/study/experience/4宿/main1.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "19.000 ns 82.61 % " "Info: Total cell delay = 19.000 ns ( 82.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 17.39 % " "Info: Total interconnect delay = 4.000 ns ( 17.39 % )" {  } {  } 0}  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "23.000 ns" { cnt6:u1|count[0] seg7_1:u2|cat0[1]~102 seg7_1:u2|cat0[1]~66 seg7_1:u2|cat0[1]~109 cat[1] } "NODE_NAME" } } }  } 0}  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "3.000 ns" { clk cnt6:u1|count[0] } "NODE_NAME" } } } { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "23.000 ns" { cnt6:u1|count[0] seg7_1:u2|cat0[1]~102 seg7_1:u2|cat0[1]~66 seg7_1:u2|cat0[1]~109 cat[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "clk ld8 15.000 ns Longest " "Info: Longest tpd from source pin clk to destination pin ld8 is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "g:/study/experience/4宿/main1.vhd" "" "" { Text "g:/study/experience/4宿/main1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.000 ns clk~6 2 COMB LC61 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC61; Fanout = 1; COMB Node = 'clk~6'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "8.000 ns" { clk clk~6 } "NODE_NAME" } } } { "g:/study/experience/4宿/main1.vhd" "" "" { Text "g:/study/experience/4宿/main1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns ld8 3 PIN PIN_34 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_34; Fanout = 0; PIN Node = 'ld8'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "4.000 ns" { clk~6 ld8 } "NODE_NAME" } } } { "g:/study/experience/4宿/main1.vhd" "" "" { Text "g:/study/experience/4宿/main1.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns 93.33 % " "Info: Total cell delay = 14.000 ns ( 93.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 6.67 % " "Info: Total interconnect delay = 1.000 ns ( 6.67 % )" {  } {  } 0}  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "15.000 ns" { clk clk~6 ld8 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk cnt\[0\] cnt6:u1\|count\[0\] 8.000 ns register " "Info: Minimum tco from clock clk to destination pin cnt\[0\] through register cnt6:u1\|count\[0\] is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "g:/study/experience/4宿/main1.vhd" "" "" { Text "g:/study/experience/4宿/main1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns cnt6:u1\|count\[0\] 2 REG LC37 32 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC37; Fanout = 32; REG Node = 'cnt6:u1\|count\[0\]'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "0.000 ns" { clk cnt6:u1|count[0] } "NODE_NAME" } } } { "g:/study/experience/4宿/cnt6.vhd" "" "" { Text "g:/study/experience/4宿/cnt6.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "3.000 ns" { clk cnt6:u1|count[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "g:/study/experience/4宿/cnt6.vhd" "" "" { Text "g:/study/experience/4宿/cnt6.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt6:u1\|count\[0\] 1 REG LC37 32 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC37; Fanout = 32; REG Node = 'cnt6:u1\|count\[0\]'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "" { cnt6:u1|count[0] } "NODE_NAME" } } } { "g:/study/experience/4宿/cnt6.vhd" "" "" { Text "g:/study/experience/4宿/cnt6.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns cnt\[0\] 2 PIN PIN_30 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'cnt\[0\]'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "4.000 ns" { cnt6:u1|count[0] cnt[0] } "NODE_NAME" } } } { "g:/study/experience/4宿/main1.vhd" "" "" { Text "g:/study/experience/4宿/main1.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0}  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "4.000 ns" { cnt6:u1|count[0] cnt[0] } "NODE_NAME" } } }  } 0}  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "3.000 ns" { clk cnt6:u1|count[0] } "NODE_NAME" } } } { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "4.000 ns" { cnt6:u1|count[0] cnt[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "btn2 ld1 15.000 ns Shortest " "Info: Shortest tpd from source pin btn2 to destination pin ld1 is 15.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns btn2 1 PIN PIN_1 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 4; PIN Node = 'btn2'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "" { btn2 } "NODE_NAME" } } } { "g:/study/experience/4宿/main1.vhd" "" "" { Text "g:/study/experience/4宿/main1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 11.000 ns btn2~2 2 COMB LC45 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC45; Fanout = 1; COMB Node = 'btn2~2'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "8.000 ns" { btn2 btn2~2 } "NODE_NAME" } } } { "g:/study/experience/4宿/main1.vhd" "" "" { Text "g:/study/experience/4宿/main1.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 15.000 ns ld1 3 PIN PIN_25 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_25; Fanout = 0; PIN Node = 'ld1'" {  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "4.000 ns" { btn2~2 ld1 } "NODE_NAME" } } } { "g:/study/experience/4宿/main1.vhd" "" "" { Text "g:/study/experience/4宿/main1.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns 93.33 % " "Info: Total cell delay = 14.000 ns ( 93.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 6.67 % " "Info: Total interconnect delay = 1.000 ns ( 6.67 % )" {  } {  } 0}  } { { "g:/study/experience/4宿/db/cnt6_cmp.qrpt" "" "" { Report "g:/study/experience/4宿/db/cnt6_cmp.qrpt" Compiler "cnt6" "UNKNOWN" "V1" "g:/study/experience/4宿/db/main1.quartus_db" { Floorplan "" "" "15.000 ns" { btn2 btn2~2 ld1 } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 26 20:21:34 2006 " "Info: Processing ended: Wed Apr 26 20:21:34 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}