cnt6.map.qmsg

数码管扫描显示控制器,同时显示0、1、2、3、4、5这6个不同的数字图形到6个数码管上。复位时所有数码管全灭。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 26 20:21:28 2006 " "Info: Processing started: Wed Apr 26 20:21:28 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off main1 -c cnt6 " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off main1 -c cnt6" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt6.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnt6.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt6-cnt6_arch " "Info: Found design unit 1: cnt6-cnt6_arch" {  } { { "g:/study/experience/4宿/cnt6.vhd" "cnt6-cnt6_arch" "" { Text "g:/study/experience/4宿/cnt6.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt6 " "Info: Found entity 1: cnt6" {  } { { "g:/study/experience/4宿/cnt6.vhd" "cnt6" "" { Text "g:/study/experience/4宿/cnt6.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg7_1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file seg7_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seg7_1-seg7_1_arch " "Info: Found design unit 1: seg7_1-seg7_1_arch" {  } { { "g:/study/experience/4宿/seg7_1.vhd" "seg7_1-seg7_1_arch" "" { Text "g:/study/experience/4宿/seg7_1.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 seg7_1 " "Info: Found entity 1: seg7_1" {  } { { "g:/study/experience/4宿/seg7_1.vhd" "seg7_1" "" { Text "g:/study/experience/4宿/seg7_1.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "main1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file main1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 main1-main1_arch " "Info: Found design unit 1: main1-main1_arch" {  } { { "g:/study/experience/4宿/main1.vhd" "main1-main1_arch" "" { Text "g:/study/experience/4宿/main1.vhd" 14 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 main1 " "Info: Found entity 1: main1" {  } { { "g:/study/experience/4宿/main1.vhd" "main1" "" { Text "g:/study/experience/4宿/main1.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count cnt6.vhd(25) " "Warning: VHDL Process Statement warning at cnt6.vhd(25): signal count is in statement, but is not in sensitivity list" {  } { { "g:/study/experience/4宿/cnt6.vhd" "" "" { Text "g:/study/experience/4宿/cnt6.vhd" 25 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "cat0 seg7_1.vhd(11) " "Warning: VHDL Process Statement warning at seg7_1.vhd(11): signal or variable cat0 may not be assigned a new value in every possible path through the Process Statement. Signal or variable cat0 holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "g:/study/experience/4宿/seg7_1.vhd" "" "" { Text "g:/study/experience/4宿/seg7_1.vhd" 11 0 0 } }  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "g:/study/experience/4宿/cnt6.vhd" "" "" { Text "g:/study/experience/4宿/cnt6.vhd" 19 -1 0 } } { "g:/study/experience/4宿/cnt6.vhd" "" "" { Text "g:/study/experience/4宿/cnt6.vhd" 19 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "cnt\[3\] GND " "Warning: Pin cnt\[3\] stuck at GND" {  } { { "g:/study/experience/4宿/main1.vhd" "" "" { Text "g:/study/experience/4宿/main1.vhd" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin clk to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "46 " "Info: Implemented 46 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "19 " "Info: Implemented 19 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "25 " "Info: Implemented 25 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 26 20:21:29 2006 " "Info: Processing ended: Wed Apr 26 20:21:29 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}