seg7_1a.tan.rpt

数码管扫描显示控制器,同时显示0、1、2、3、4、5这6个不同的数字图形到6个数码管上。复位时所有数码管全灭。

; N/A   ; None         ; 8.000 ns   ; cat[0]~reg0 ; cat[0] ; clk        ;
; N/A   ; None         ; 8.000 ns   ; cat[1]~reg0 ; cat[1] ; clk        ;
+-------+--------------+------------+-------------+--------+------------+


+-------------------------------------------------------------------------+
; th                                                                      ;
+---------------+-------------+-----------+------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To          ; To Clock ;
+---------------+-------------+-----------+------+-------------+----------+
; N/A           ; None        ; -3.000 ns ; btn2 ; count1[0]   ; clk      ;
; N/A           ; None        ; -3.000 ns ; btn2 ; count1[1]   ; clk      ;
; N/A           ; None        ; -3.000 ns ; btn2 ; count1[2]   ; clk      ;
; N/A           ; None        ; -3.000 ns ; btn2 ; cat[1]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; btn2 ; cat[0]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; btn2 ; cat[3]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; btn2 ; cat[2]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; btn2 ; cat[5]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; btn2 ; cat[4]~reg0 ; clk      ;
; N/A           ; None        ; -3.000 ns ; btn2 ; num[2]      ; clk      ;
; N/A           ; None        ; -3.000 ns ; btn2 ; num[1]      ; clk      ;
; N/A           ; None        ; -3.000 ns ; btn2 ; num[0]      ; clk      ;
+---------------+-------------+-----------+------+-------------+----------+


+---------------------------------------------------------------------------------------+
; Minimum tco                                                                           ;
+---------------+------------------+----------------+-------------+--------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From        ; To     ; From Clock ;
+---------------+------------------+----------------+-------------+--------+------------+
; N/A           ; None             ; 8.000 ns       ; cat[1]~reg0 ; cat[1] ; clk        ;
; N/A           ; None             ; 8.000 ns       ; cat[0]~reg0 ; cat[0] ; clk        ;
; N/A           ; None             ; 8.000 ns       ; cat[3]~reg0 ; cat[3] ; clk        ;
; N/A           ; None             ; 8.000 ns       ; cat[2]~reg0 ; cat[2] ; clk        ;
; N/A           ; None             ; 8.000 ns       ; cat[5]~reg0 ; cat[5] ; clk        ;
; N/A           ; None             ; 8.000 ns       ; cat[4]~reg0 ; cat[4] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[0]      ; lcd[2] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[2]      ; lcd[2] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[1]      ; lcd[0] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[2]      ; lcd[0] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[0]      ; lcd[5] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[1]      ; lcd[5] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[2]      ; lcd[5] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[0]      ; lcd[4] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[1]      ; lcd[4] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[2]      ; lcd[4] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[0]      ; lcd[3] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[1]      ; lcd[3] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[2]      ; lcd[3] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[0]      ; lcd[1] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[1]      ; lcd[1] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[2]      ; lcd[1] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[0]      ; lcd[6] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[1]      ; lcd[6] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; num[2]      ; lcd[6] ; clk        ;
+---------------+------------------+----------------+-------------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Sat Apr 29 23:45:30 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off main -c seg7_1a
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: Clock clk has Internal fmax of 71.43 MHz between source register count[0] and destination register num[0] (period= 14.0 ns)
    Info: + Longest register to register delay is 9.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC67; Fanout = 29; REG Node = 'count[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC33; Fanout = 1; COMB Node = 'Mux~1211'
        Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC34; Fanout = 7; REG Node = 'num[0]'
        Info: Total cell delay = 7.000 ns ( 77.78 % )
        Info: Total interconnect delay = 2.000 ns ( 22.22 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock clk to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC34; Fanout = 7; REG Node = 'num[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock clk to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC67; Fanout = 29; REG Node = 'count[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register count1[0] (data pin = btn2, clock pin = clk) is 11.000 ns
    Info: + Longest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 33; PIN Node = 'btn2'
        Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC65; Fanout = 23; REG Node = 'count1[0]'
        Info: Total cell delay = 9.000 ns ( 90.00 % )
        Info: Total interconnect delay = 1.000 ns ( 10.00 % )
    Info: + Micro setup delay of destination is 4.000 ns
    Info: - Shortest clock path from clock clk to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC65; Fanout = 23; REG Node = 'count1[0]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: tco from clock clk to destination pin lcd[6] through register num[2] is 17.000 ns
    Info: + Longest clock path from clock clk to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC55; Fanout = 9; REG Node = 'num[2]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 13.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC55; Fanout = 9; REG Node = 'num[2]'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC8; Fanout = 1; COMB Node = 'seg7_1a:u1|i[3]~105'
        Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_9; Fanout = 0; PIN Node = 'lcd[6]'
        Info: Total cell delay = 11.000 ns ( 84.62 % )
        Info: Total interconnect delay = 2.000 ns ( 15.38 % )
Info: th for register count1[0] (data pin = btn2, clock pin = clk) is -3.000 ns
    Info: + Longest clock path from clock clk to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC65; Fanout = 23; REG Node = 'count1[0]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 4.000 ns
    Info: - Shortest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 33; PIN Node = 'btn2'
        Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC65; Fanout = 23; REG Node = 'count1[0]'
        Info: Total cell delay = 9.000 ns ( 90.00 % )
        Info: Total interconnect delay = 1.000 ns ( 10.00 % )
Info: Minimum tco from clock clk to destination pin cat[1] through register cat[1]~reg0 is 8.000 ns
    Info: + Shortest clock path from clock clk to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 33; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC51; Fanout = 1; REG Node = 'cat[1]~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Shortest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC51; Fanout = 1; REG Node = 'cat[1]~reg0'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'cat[1]'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Apr 29 23:45:31 2006
    Info: Elapsed time: 00:00:00