main1.vhd

来自「数码管扫描显示控制器,同时显示0、1、2、3、4、5这6个不同的数字图形到6个数」· VHDL 代码 · 共 35 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity main1 is
 port(clk,btn2:in std_logic;
 cat:out std_logic_vector(5 downto 0);
 ld1,ld8:out std_logic;
 cnt:out std_logic_vector(3 downto 0);
 lcd:out std_logic_vector(6 downto 0));
end main1;

architecture main1_arch of main1 is

component cnt6
port (clk0,btn20:in std_logic;
cnt0:out std_logic_vector(3 downto 0));
end component;

component seg7_1
port(h:in std_logic_vector(3 downto 0);
     i:out std_logic_vector(6 downto 0);
     cat0:out std_logic_vector(5 downto 0));
     end component;
signal u:std_logic_vector(3 downto 0);
   

begin 
u1:cnt6 port map(clk0=>clk,btn20=>btn2,cnt0=>u);
u2:seg7_1 port map (h=>u,i=>lcd,cat0=>cat);
cnt<=u;
ld8<=clk;
ld1<=btn2;
end;