cnt6.tan.rpt

数码管扫描显示控制器,同时显示0、1、2、3、4、5这6个不同的数字图形到6个数码管上。复位时所有数码管全灭。

; N/A   ; None         ; 8.000 ns   ; cnt6:u1|count[0] ; cnt[0] ; clk        ;
+-------+--------------+------------+------------------+--------+------------+


+----------------------------------------------------------+
; tpd                                                      ;
+-------+-------------------+-----------------+------+-----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To  ;
+-------+-------------------+-----------------+------+-----+
; N/A   ; None              ; 15.000 ns       ; clk  ; ld8 ;
; N/A   ; None              ; 15.000 ns       ; btn2 ; ld1 ;
+-------+-------------------+-----------------+------+-----+


+--------------------------------------------------------------------------------------------+
; Minimum tco                                                                                ;
+---------------+------------------+----------------+------------------+--------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From             ; To     ; From Clock ;
+---------------+------------------+----------------+------------------+--------+------------+
; N/A           ; None             ; 8.000 ns       ; cnt6:u1|count[0] ; cnt[0] ; clk        ;
; N/A           ; None             ; 8.000 ns       ; cnt6:u1|count[2] ; cnt[2] ; clk        ;
; N/A           ; None             ; 8.000 ns       ; cnt6:u1|count[1] ; cnt[1] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[1] ; lcd[3] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[2] ; lcd[3] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[0] ; lcd[3] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[2] ; lcd[2] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[0] ; lcd[2] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[1] ; lcd[6] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[2] ; lcd[6] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[0] ; lcd[6] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[1] ; lcd[4] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[2] ; lcd[4] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[0] ; lcd[4] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[1] ; lcd[1] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[2] ; lcd[1] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[0] ; lcd[1] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[1] ; lcd[0] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[2] ; lcd[0] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[1] ; lcd[5] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[2] ; lcd[5] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[0] ; lcd[5] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[2] ; cat[3] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[1] ; cat[2] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[2] ; cat[2] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[0] ; cat[2] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[1] ; cat[0] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[2] ; cat[0] ; clk        ;
; N/A           ; None             ; 17.000 ns      ; cnt6:u1|count[0] ; cat[0] ; clk        ;
; N/A           ; None             ; 18.000 ns      ; cnt6:u1|count[1] ; cat[4] ; clk        ;
; N/A           ; None             ; 18.000 ns      ; cnt6:u1|count[2] ; cat[4] ; clk        ;
; N/A           ; None             ; 18.000 ns      ; cnt6:u1|count[0] ; cat[4] ; clk        ;
; N/A           ; None             ; 18.000 ns      ; cnt6:u1|count[1] ; cat[3] ; clk        ;
; N/A           ; None             ; 18.000 ns      ; cnt6:u1|count[0] ; cat[3] ; clk        ;
; N/A           ; None             ; 26.000 ns      ; cnt6:u1|count[1] ; cat[1] ; clk        ;
; N/A           ; None             ; 26.000 ns      ; cnt6:u1|count[2] ; cat[1] ; clk        ;
; N/A           ; None             ; 26.000 ns      ; cnt6:u1|count[0] ; cat[1] ; clk        ;
; N/A           ; None             ; 27.000 ns      ; cnt6:u1|count[1] ; cat[5] ; clk        ;
; N/A           ; None             ; 27.000 ns      ; cnt6:u1|count[2] ; cat[5] ; clk        ;
; N/A           ; None             ; 27.000 ns      ; cnt6:u1|count[0] ; cat[5] ; clk        ;
+---------------+------------------+----------------+------------------+--------+------------+


+------------------------------------------------------------------+
; Minimum tpd                                                      ;
+---------------+-------------------+-----------------+------+-----+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From ; To  ;
+---------------+-------------------+-----------------+------+-----+
; N/A           ; None              ; 15.000 ns       ; btn2 ; ld1 ;
; N/A           ; None              ; 15.000 ns       ; clk  ; ld8 ;
+---------------+-------------------+-----------------+------+-----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Wed Apr 26 20:21:34 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off main1 -c cnt6
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Found combinational loop of 2 nodes
    Info: Node seg7_1:u2|cat0[3]~58
    Info: Node seg7_1:u2|cat0[3]~92
Info: Found combinational loop of 2 nodes
    Info: Node seg7_1:u2|cat0[4]~54
    Info: Node seg7_1:u2|cat0[4]~84
Info: Found combinational loop of 2 nodes
    Info: Node seg7_1:u2|cat0[5]~50
    Info: Node seg7_1:u2|cat0[5]~79
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: Clock clk has Internal fmax of 76.92 MHz between source register cnt6:u1|count[0] and destination register cnt6:u1|count[1] (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC37; Fanout = 32; REG Node = 'cnt6:u1|count[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC38; Fanout = 40; REG Node = 'cnt6:u1|count[1]'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock clk to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC38; Fanout = 40; REG Node = 'cnt6:u1|count[1]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock clk to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC37; Fanout = 32; REG Node = 'cnt6:u1|count[0]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock clk to destination pin cat[1] through register cnt6:u1|count[0] is 27.000 ns
    Info: + Longest clock path from clock clk to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC37; Fanout = 32; REG Node = 'cnt6:u1|count[0]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 23.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC37; Fanout = 32; REG Node = 'cnt6:u1|count[0]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC62; Fanout = 1; COMB Node = 'seg7_1:u2|cat0[1]~102'
        Info: 3: + IC(0.000 ns) + CELL(2.000 ns) = 10.000 ns; Loc. = LC63; Fanout = 4; COMB Node = 'seg7_1:u2|cat0[1]~66'
        Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC57; Fanout = 1; COMB Node = 'seg7_1:u2|cat0[1]~109'
        Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 23.000 ns; Loc. = PIN_36; Fanout = 0; PIN Node = 'cat[1]'
        Info: Total cell delay = 19.000 ns ( 82.61 % )
        Info: Total interconnect delay = 4.000 ns ( 17.39 % )
Info: Longest tpd from source pin clk to destination pin ld8 is 15.000 ns
    Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'
    Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC61; Fanout = 1; COMB Node = 'clk~6'
    Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_34; Fanout = 0; PIN Node = 'ld8'
    Info: Total cell delay = 14.000 ns ( 93.33 % )
    Info: Total interconnect delay = 1.000 ns ( 6.67 % )
Info: Minimum tco from clock clk to destination pin cnt[0] through register cnt6:u1|count[0] is 8.000 ns
    Info: + Shortest clock path from clock clk to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC37; Fanout = 32; REG Node = 'cnt6:u1|count[0]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Shortest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC37; Fanout = 32; REG Node = 'cnt6:u1|count[0]'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'cnt[0]'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: Shortest tpd from source pin btn2 to destination pin ld1 is 15.000 ns
    Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 4; PIN Node = 'btn2'
    Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC45; Fanout = 1; COMB Node = 'btn2~2'
    Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 15.000 ns; Loc. = PIN_25; Fanout = 0; PIN Node = 'ld1'
    Info: Total cell delay = 14.000 ns ( 93.33 % )
    Info: Total interconnect delay = 1.000 ns ( 6.67 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Apr 26 20:21:34 2006
    Info: Elapsed time: 00:00:00