4adder.vhd

Quartus2实现的四位进制并行加法器 用VHDL语言实现

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--实验题号   : lab2-1
--项目名称   : 四位加法器(超前进位)
--文件名     : 4Adder.vhd
--作者       : 李若珍
--班号.      : 计64 
--创建日期   : 2008-04-10
--目标芯片   : EP1C6Q240C8
--电路模式   : 模式1
--演示说明   : 按键1输入加数
--             按键2输入被加数
--             数码管5显示运算结果的低位，6显示高位
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Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Four_Adder is
port(
f1,f2:in std_logic_vector(1 to 4);--两位输入
c0:in std_logic;--低级进位输入
cout_low:out std_logic_vector(1 to 4);--输出低位
cout_high:out std_logic);--输出高位
end entity;

architecture Four_Add of Four_Adder is

component Whole_Adder 
port(
ain,bin,cin:in std_logic;
cout,fout:out std_logic);
end component;


signal P1,P2,P3,P4:std_logic;
signal G1,G2,G3,G4:std_logic;
signal temp1,temp2,temp3:std_logic;

begin
G1<=f1(1) and f2(1);
G2<=f1(2) and f2(2);
G3<=f1(3) and f2(3);
G4<=f1(4) and f2(4);
P1<=f1(1) or f2(1);
P2<=f1(2) or f2(2);
P3<=f1(3) or f2(3);
P4<=f1(4) or f2(4);

temp1<=NOT((NOT P1) OR ((NOT G1)AND(NOT C0)));--超前进位
temp2<=NOT((NOT P2) OR ((NOT G2) AND (NOT P1)) OR ((NOT G2) AND (NOT G1) AND (NOT C0)));
temp3<=NOT( (NOT P3) OR ((NOT G3) AND (NOT P2)) OR ((NOT G3) AND (NOT G2) AND (NOT P1)) OR ((NOT G3) AND (NOT G2) AND (NOT G1) AND (NOT C0)));
cout_high<=NOT ( (NOT P4) OR ((NOT G4) AND (NOT P3)) OR ((NOT G4) AND( NOT G3) AND (NOT P2)) OR ((NOT G4) AND (NOT G3) AND (NOT G2) AND( NOT P1))
OR ( (NOT G4) AND (NOT G3) AND (NOT G2) AND (NOT G1) AND (NOT C0)));


u1: Whole_Adder port map
(ain=>f1(1),bin=>f2(1),cin=>c0,fout=>cout_low(1));

u2: Whole_Adder port map
(ain=>f1(2),bin=>f2(2),cin=>temp1,fout=>cout_low(2));

u3: Whole_Adder port map
(ain=>f1(3),bin=>f2(3),cin=>temp2,fout=>cout_low(3));

u4: Whole_Adder port map
(ain=>f1(4),bin=>f2(4),cin=>temp3,fout=>cout_low(4));

end Four_Add;







Library IEEE;
use ieee.std_logic_1164.all;

entity Half_Adder is
PORT (
a,b:in std_logic;
c,f:out std_logic);
end entity;

architecture behave of Half_Adder is
begin
    f <= not (a xor (not b));
    c <= a and b;

end behave;

Library IEEE;
use ieee.std_logic_1164.all;

entity Whole_Adder is
port(
ain,bin,cin:in std_logic;
cout,fout:out std_logic);
end entity;

architecture Add of Whole_Adder is
component Half_Adder
PORT (
a,b:in std_logic;
c,f:out std_logic);
end component;

signal Temp1,Temp2,Temp3:std_logic;
begin
u1:Half_Adder port map
(a=>ain,b=>bin,c=>Temp1,f=>Temp2);
u2:Half_Adder port map
(a=>Temp2,b=>cin,c=>Temp3,f=>fout);
cout<=Temp1 or Temp3;

end Add;