📄 4adder.tan.rpt
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Classic Timing Analyzer report for 4Adder
Mon Mar 31 09:19:26 2008
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+-----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+-----------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 16.243 ns ; c0 ; cout_high ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+-----------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-------------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+-------+-------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+-------+-------------+
; N/A ; None ; 16.243 ns ; c0 ; cout_high ;
; N/A ; None ; 15.800 ns ; c0 ; cout_low[4] ;
; N/A ; None ; 14.693 ns ; c0 ; cout_low[3] ;
; N/A ; None ; 14.435 ns ; c0 ; cout_low[2] ;
; N/A ; None ; 13.840 ns ; c0 ; cout_low[1] ;
; N/A ; None ; 13.489 ns ; f1[1] ; cout_high ;
; N/A ; None ; 13.206 ns ; f1[2] ; cout_high ;
; N/A ; None ; 13.046 ns ; f1[1] ; cout_low[4] ;
; N/A ; None ; 12.991 ns ; f2[1] ; cout_high ;
; N/A ; None ; 12.763 ns ; f1[2] ; cout_low[4] ;
; N/A ; None ; 12.583 ns ; f2[2] ; cout_high ;
; N/A ; None ; 12.548 ns ; f2[1] ; cout_low[4] ;
; N/A ; None ; 12.140 ns ; f2[2] ; cout_low[4] ;
; N/A ; None ; 12.017 ns ; f2[3] ; cout_high ;
; N/A ; None ; 11.939 ns ; f1[1] ; cout_low[3] ;
; N/A ; None ; 11.803 ns ; f1[3] ; cout_high ;
; N/A ; None ; 11.681 ns ; f1[1] ; cout_low[2] ;
; N/A ; None ; 11.656 ns ; f1[2] ; cout_low[3] ;
; N/A ; None ; 11.574 ns ; f2[3] ; cout_low[4] ;
; N/A ; None ; 11.485 ns ; f2[4] ; cout_high ;
; N/A ; None ; 11.441 ns ; f2[1] ; cout_low[3] ;
; N/A ; None ; 11.395 ns ; f1[2] ; cout_low[2] ;
; N/A ; None ; 11.360 ns ; f1[3] ; cout_low[4] ;
; N/A ; None ; 11.183 ns ; f2[1] ; cout_low[2] ;
; N/A ; None ; 11.178 ns ; f1[4] ; cout_high ;
; N/A ; None ; 11.087 ns ; f1[1] ; cout_low[1] ;
; N/A ; None ; 11.047 ns ; f2[4] ; cout_low[4] ;
; N/A ; None ; 11.033 ns ; f2[2] ; cout_low[3] ;
; N/A ; None ; 11.024 ns ; f2[3] ; cout_low[3] ;
; N/A ; None ; 10.806 ns ; f1[3] ; cout_low[3] ;
; N/A ; None ; 10.776 ns ; f2[2] ; cout_low[2] ;
; N/A ; None ; 10.738 ns ; f1[4] ; cout_low[4] ;
; N/A ; None ; 10.586 ns ; f2[1] ; cout_low[1] ;
+-------+-------------------+-----------------+-------+-------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
Info: Processing started: Mon Mar 31 09:19:25 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off 4Adder -c 4Adder --timing_analysis_only
Info: Longest tpd from source pin "c0" to destination pin "cout_high" is 16.243 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_169; Fanout = 2; PIN Node = 'c0'
Info: 2: + IC(7.861 ns) + CELL(0.590 ns) = 9.920 ns; Loc. = LC_X2_Y20_N3; Fanout = 2; COMB Node = 'Whole_Adder:u4|Half_Adder:u2|f~361'
Info: 3: + IC(0.440 ns) + CELL(0.114 ns) = 10.474 ns; Loc. = LC_X2_Y20_N8; Fanout = 2; COMB Node = 'Whole_Adder:u4|Half_Adder:u2|f~362'
Info: 4: + IC(0.411 ns) + CELL(0.442 ns) = 11.327 ns; Loc. = LC_X2_Y20_N5; Fanout = 2; COMB Node = 'Whole_Adder:u4|Half_Adder:u2|f~363'
Info: 5: + IC(0.442 ns) + CELL(0.114 ns) = 11.883 ns; Loc. = LC_X2_Y20_N4; Fanout = 1; COMB Node = 'cout_high~112'
Info: 6: + IC(2.236 ns) + CELL(2.124 ns) = 16.243 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'cout_high'
Info: Total cell delay = 4.853 ns ( 29.88 % )
Info: Total interconnect delay = 11.390 ns ( 70.12 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Allocated 104 megabytes of memory during processing
Info: Processing ended: Mon Mar 31 09:19:26 2008
Info: Elapsed time: 00:00:01
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