📄 st72321.h
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#define P_ACCON PD_DR.field.B5
#define P_KEY2 PD_DR.field.B4
#define P_KEY1 PD_DR.field.B3
#define P_SMTER PD_DR.field.B2
#define P_QUALITY PD_DR.field.B1
EXTR UByteField PD_DDR;
#define D_RDSQUAL PD_DDR.field.B6
#define D_ACCON PD_DDR.field.B5
#define D_KEY2 PD_DDR.field.B4
#define D_KEY1 PD_DDR.field.B3
#define D_SMTER PD_DDR.field.B2
#define D_QUALITY PD_DDR.field.B1
EXTR UByteField PD_OR; /* option register */
#define O_RDSQUAL PD_OR.field.B6
#define O_ACCON PD_OR.field.B5
#define O_KEY2 PD_OR.field.B4
#define O_KEY1 PD_OR.field.B3
#define O_SMTER PD_OR.field.B2
#define O_QUALITY PD_OR.field.B1
#pragma DATA_SEG SHORT ST7_PE
EXTR UByteField PE_DR;
#define P_AFSCON PE_DR.field.B0
#define P_SD PE_DR.field.B3
#define P_AMUTE PE_DR.field.B4
EXTR UByteField PE_DDR;
#define D_AFSCON PE_DDR.field.B0
#define D_SD PE_DDR.field.B3
#define D_AMUTE PE_DDR.field.B4
EXTR UByteField PE_OR; /* option register */
#define O_AFSCON PE_OR.field.B0
#define O_SD PE_OR.field.B3
#define O_AMUTE PE_OR.field.B4
#pragma DATA_SEG SHORT ST7_PF
EXTR UByteField PF_DR;
#define P_PWRON PF_DR.field.B2
EXTR UByteField PF_DDR;
#define D_PWRON PF_DDR.field.B2
EXTR UByteField PF_OR; /* option register */
#define O_PWRON PF_OR.field.B2
/*--------------------------------------------------------------------------
ST72321 I2C Internal Registers
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_I2C
extern volatile unsigned char I2CCR; // Control Register
extern volatile unsigned char I2CSR1; // Status Register 1
extern volatile unsigned char I2CSR2; // Status Register 2
extern volatile unsigned char I2CCCR; // Clock Control Register
extern volatile unsigned char I2COAR1; // Own Address Register 1
extern volatile unsigned char I2COAR2; // Own Address Register 2
extern volatile unsigned char I2CDR; // I2C Data Register
/*--------------------------------------------------------------------------
ST72321 SPI Internal Registers
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_SPI
extern volatile unsigned char SPI1_DR; /* data register */
extern volatile unsigned char SPI1_CR; /* control register */
extern volatile unsigned char SPI1_SR; /* status register */
/*--------------------------------------------------------------------------
ST72321 ITC Internal Registers
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_ITC
extern volatile unsigned char ISPR0; /* interrupt software priority reg0*/
extern volatile unsigned char ISPR1; /* interrupt software priority reg1*/
extern volatile unsigned char ISPR2; /* interrupt software priority reg2*/
extern volatile unsigned char ISPR3; /* interrupt software priority reg3*/
extern volatile unsigned char EICR; // External Interrupt Control Register
/*--------------------------------------------------------------------------
ST72321 Flash control/status reg
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_FLASH
extern volatile unsigned char FCSR; // Flash Control status reg
/*--------------------------------------------------------------------------
ST72321 WATCHDOG reg
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_WDG
extern volatile unsigned char WDGCR; /* WatchDog Control Register */
extern volatile unsigned char SICSR; // System Integrity Control/Status Register
/*--------------------------------------------------------------------------
ST72321 Main Clock control/status reg
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_MCC
extern volatile unsigned char MCCSR; // Main clock control/status reg
extern volatile unsigned char MCCBCR; // Main clock cntrl/beep control reg
/*--------------------------------------------------------------------------
ST72321 Timer A Internal Registers
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_TIMA
extern volatile unsigned char TIM1_CR2; /* control register 2 */
extern volatile unsigned char TIM1_CR1; /* control register 1 */
extern volatile unsigned char TIM1_SR; /* status register */
extern volatile unsigned char TIM1_IC1H; /* input capture 1 high */
extern volatile unsigned char TIM1_IC1L; /* input capture 1 low */
extern volatile unsigned char TIM1_OC1H; /* output compare 1 high */
extern volatile unsigned char TIM1_OC1L; /* output compare 1 low */
extern volatile unsigned char TIM1_CNT; /* counter high */
extern volatile unsigned char TIM1_CNTL; /* counter low */
extern volatile unsigned char TIM1_ACH; /* alternate counter high */
extern volatile unsigned char TIM1_ACL; /* alternate counter low */
extern volatile unsigned char TIM1_IC2H; /* input capture 2 high */
extern volatile unsigned char TIM1_IC2L; /* input capture 2 low */
extern volatile unsigned char TIM1_OC2H; /* output compare 2 high */
extern volatile unsigned char TIM1_OC2L; /* output compare 2 low */
/*--------------------------------------------------------------------------
ST72321 Timer B Internal Registers
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_TIMB
extern volatile unsigned char TIM2_CR2; /* control register 2 */
extern volatile unsigned char TIM2_CR1; /* control register 1 */
extern volatile unsigned char TIM2_SR; /* status register */
extern volatile unsigned char TIM2_IC1H; /* input capture 1 high */
extern volatile unsigned char TIM2_IC1L; /* input capture 1 low */
extern volatile unsigned char TIM2_OC1H; /* output compare 1 high */
extern volatile unsigned char TIM2_OC1L; /* output compare 1 low */
extern volatile unsigned char TIM2_CNT; /* counter high */
extern volatile unsigned char TIM2_CNTL; /* counter low */
extern volatile unsigned char TIM2_ACH; /* alternate counter high */
extern volatile unsigned char TIM2_ACL; /* alternate counter low */
extern volatile unsigned char TIM2_IC2H; /* input capture 2 high */
extern volatile unsigned char TIM2_IC2L; /* input capture 2 low */
extern volatile unsigned char TIM2_OC2H; /* output compare 2 high */
extern volatile unsigned char TIM2_OC2L; /* output compare 2 low */
/*--------------------------------------------------------------------------
ST72321 SCI Internal Registers
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_SCI
extern volatile unsigned char SCI_SCSR; /* status register */
extern volatile unsigned char SCI_SCDR; /* data register */
extern volatile unsigned char SCI_SCBRR; /* baud rate register */
extern volatile unsigned char SCI_SCCR1; /* control register 1 */
extern volatile unsigned char SCI_SCCR2; /* control register 2 */
extern volatile unsigned char SCI_PSCBRR; /* rx baud rate register */
extern volatile unsigned char SCI_PRETEST; /* reserved */
extern volatile unsigned char SCI_PSCBRT; /* tx baud rate register */
/*--------------------------------------------------------------------------
ST72321 ADC Internal Registers
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_ADC
//extern volatile unsigned char ADCCSR; // control/status register
extern volatile unsigned char ADC_CR; /* control/status register */
extern volatile unsigned char ADC_DR; /* data register */
//extern volatile unsigned char ADCDRH; // data high register
extern volatile unsigned char ADCDRL; // data low register
/*--------------------------------------------------------------------------
ST72321 PWM ART Internal Registers
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_PWMART
extern volatile unsigned char PWMDCR3; // PWM AR duty cycle register 3
extern volatile unsigned char PWMDCR2; // PWM AR duty cycle register 2
extern volatile unsigned char PWMDCR1; // PWM AR duty cycle register 1
extern volatile unsigned char PWMDCR0; // PWM AR duty cycle register 0
extern volatile unsigned char PWMCR; // PWM AR timer cntrl register
extern volatile unsigned char ARTCSR; // autoreload timer cntrl status reg
extern volatile unsigned char ARTCAR; // autoreload timer counter access reg
extern volatile unsigned char ARTARR; // autoreload timer autoreload reg
extern volatile unsigned char ARTICCSR; // AR timer input capture control/status reg
extern volatile unsigned char ARTICR1; // AR timer input capture reg 1
extern volatile unsigned char ARTICR2; // AR timer input capture reg 2
#pragma DATA_SEG DEFAULT
/*** (c) 2005 STMicroelectronics ****************** END OF FILE ***/
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