📄 io_map.h
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#define ICSSC_CLKST_MASK 0x04
/*** TPMSC - TPM Timer Status and Control Register; 0x00000040 ***/
typedef union {
byte Byte;
struct {
byte PS0 :1; /* Prescale Divisor Select Bit 0 */
byte PS1 :1; /* Prescale Divisor Select Bit 1 */
byte PS2 :1; /* Prescale Divisor Select Bit 2 */
byte CLKSA :1; /* Clock Source Select A */
byte CLKSB :1; /* Clock Source Select B */
byte CPWMS :1; /* Center-Aligned PWM Select */
byte TOIE :1; /* Timer Overflow Interrupt Enable */
byte TOF :1; /* Timer Overflow Flag */
} Bits;
struct {
byte grpPS :3;
byte grpCLKSx :2;
byte :1;
byte :1;
byte :1;
} MergedBits;
} TPMSCSTR;
extern volatile TPMSCSTR _TPMSC @0x00000040;
#define TPMSC _TPMSC.Byte
#define TPMSC_PS0 _TPMSC.Bits.PS0
#define TPMSC_PS1 _TPMSC.Bits.PS1
#define TPMSC_PS2 _TPMSC.Bits.PS2
#define TPMSC_CLKSA _TPMSC.Bits.CLKSA
#define TPMSC_CLKSB _TPMSC.Bits.CLKSB
#define TPMSC_CPWMS _TPMSC.Bits.CPWMS
#define TPMSC_TOIE _TPMSC.Bits.TOIE
#define TPMSC_TOF _TPMSC.Bits.TOF
#define TPMSC_PS _TPMSC.MergedBits.grpPS
#define TPMSC_CLKSx _TPMSC.MergedBits.grpCLKSx
#define TPMSC_PS0_MASK 0x01
#define TPMSC_PS1_MASK 0x02
#define TPMSC_PS2_MASK 0x04
#define TPMSC_CLKSA_MASK 0x08
#define TPMSC_CLKSB_MASK 0x10
#define TPMSC_CPWMS_MASK 0x20
#define TPMSC_TOIE_MASK 0x40
#define TPMSC_TOF_MASK 0x80
#define TPMSC_PS_MASK 0x07
#define TPMSC_PS_BITNUM 0x00
#define TPMSC_CLKSx_MASK 0x18
#define TPMSC_CLKSx_BITNUM 0x03
/*** TPMCNT - TPM Counter Register; 0x00000041 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** TPMCNTH - TPM Counter Register High; 0x00000041 ***/
union {
byte Byte;
} TPMCNTHSTR;
#define TPMCNTH _TPMCNT.Overlap_STR.TPMCNTHSTR.Byte
/*** TPMCNTL - TPM Counter Register Low; 0x00000042 ***/
union {
byte Byte;
} TPMCNTLSTR;
#define TPMCNTL _TPMCNT.Overlap_STR.TPMCNTLSTR.Byte
} Overlap_STR;
} TPMCNTSTR;
extern volatile TPMCNTSTR _TPMCNT @0x00000041;
#define TPMCNT _TPMCNT.Word
/*** TPMMOD - TPM Timer Counter Modulo Register; 0x00000043 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** TPMMODH - TPM Timer Counter Modulo Register High; 0x00000043 ***/
union {
byte Byte;
} TPMMODHSTR;
#define TPMMODH _TPMMOD.Overlap_STR.TPMMODHSTR.Byte
/*** TPMMODL - TPM Timer Counter Modulo Register Low; 0x00000044 ***/
union {
byte Byte;
} TPMMODLSTR;
#define TPMMODL _TPMMOD.Overlap_STR.TPMMODLSTR.Byte
} Overlap_STR;
} TPMMODSTR;
extern volatile TPMMODSTR _TPMMOD @0x00000043;
#define TPMMOD _TPMMOD.Word
/*** TPMC0SC - TPM Timer Channel 0 Status and Control Register; 0x00000045 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte ELS0A :1; /* Edge/Level Select Bit A */
byte ELS0B :1; /* Edge/Level Select Bit B */
byte MS0A :1; /* Mode Select A for TPM Channel 0 */
byte MS0B :1; /* Mode Select B for TPM Channel 0 */
byte CH0IE :1; /* Channel 0 Interrupt Enable */
byte CH0F :1; /* Channel 0 Flag */
} Bits;
struct {
byte :1;
byte :1;
byte grpELS0x :2;
byte grpMS0x :2;
byte :1;
byte :1;
} MergedBits;
} TPMC0SCSTR;
extern volatile TPMC0SCSTR _TPMC0SC @0x00000045;
#define TPMC0SC _TPMC0SC.Byte
#define TPMC0SC_ELS0A _TPMC0SC.Bits.ELS0A
#define TPMC0SC_ELS0B _TPMC0SC.Bits.ELS0B
#define TPMC0SC_MS0A _TPMC0SC.Bits.MS0A
#define TPMC0SC_MS0B _TPMC0SC.Bits.MS0B
#define TPMC0SC_CH0IE _TPMC0SC.Bits.CH0IE
#define TPMC0SC_CH0F _TPMC0SC.Bits.CH0F
#define TPMC0SC_ELS0x _TPMC0SC.MergedBits.grpELS0x
#define TPMC0SC_MS0x _TPMC0SC.MergedBits.grpMS0x
#define TPMC0SC_ELS0A_MASK 0x04
#define TPMC0SC_ELS0B_MASK 0x08
#define TPMC0SC_MS0A_MASK 0x10
#define TPMC0SC_MS0B_MASK 0x20
#define TPMC0SC_CH0IE_MASK 0x40
#define TPMC0SC_CH0F_MASK 0x80
#define TPMC0SC_ELS0x_MASK 0x0C
#define TPMC0SC_ELS0x_BITNUM 0x02
#define TPMC0SC_MS0x_MASK 0x30
#define TPMC0SC_MS0x_BITNUM 0x04
/*** TPMC0V - TPM Timer Channel 0 Value Register; 0x00000046 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** TPMC0VH - TPM Timer Channel 0 Value Register High; 0x00000046 ***/
union {
byte Byte;
} TPMC0VHSTR;
#define TPMC0VH _TPMC0V.Overlap_STR.TPMC0VHSTR.Byte
/*** TPMC0VL - TPM Timer Channel 0 Value Register Low; 0x00000047 ***/
union {
byte Byte;
} TPMC0VLSTR;
#define TPMC0VL _TPMC0V.Overlap_STR.TPMC0VLSTR.Byte
} Overlap_STR;
} TPMC0VSTR;
extern volatile TPMC0VSTR _TPMC0V @0x00000046;
#define TPMC0V _TPMC0V.Word
/*** TPMC1SC - TPM Timer Channel 1 Status and Control Register; 0x00000048 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte ELS1A :1; /* Edge/Level Select Bit A */
byte ELS1B :1; /* Edge/Level Select Bit B */
byte MS1A :1; /* Mode Select A for TPM Channel 1 */
byte MS1B :1; /* Mode Select B for TPM Channel 1 */
byte CH1IE :1; /* Channel 1 Interrupt Enable */
byte CH1F :1; /* Channel 1 Flag */
} Bits;
struct {
byte :1;
byte :1;
byte grpELS1x :2;
byte grpMS1x :2;
byte :1;
byte :1;
} MergedBits;
} TPMC1SCSTR;
extern volatile TPMC1SCSTR _TPMC1SC @0x00000048;
#define TPMC1SC _TPMC1SC.Byte
#define TPMC1SC_ELS1A _TPMC1SC.Bits.ELS1A
#define TPMC1SC_ELS1B _TPMC1SC.Bits.ELS1B
#define TPMC1SC_MS1A _TPMC1SC.Bits.MS1A
#define TPMC1SC_MS1B _TPMC1SC.Bits.MS1B
#define TPMC1SC_CH1IE _TPMC1SC.Bits.CH1IE
#define TPMC1SC_CH1F _TPMC1SC.Bits.CH1F
#define TPMC1SC_ELS1x _TPMC1SC.MergedBits.grpELS1x
#define TPMC1SC_MS1x _TPMC1SC.MergedBits.grpMS1x
#define TPMC1SC_ELS1A_MASK 0x04
#define TPMC1SC_ELS1B_MASK 0x08
#define TPMC1SC_MS1A_MASK 0x10
#define TPMC1SC_MS1B_MASK 0x20
#define TPMC1SC_CH1IE_MASK 0x40
#define TPMC1SC_CH1F_MASK 0x80
#define TPMC1SC_ELS1x_MASK 0x0C
#define TPMC1SC_ELS1x_BITNUM 0x02
#define TPMC1SC_MS1x_MASK 0x30
#define TPMC1SC_MS1x_BITNUM 0x04
/*** TPMC1V - TPM Timer Channel 1 Value Register; 0x00000049 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** TPMC1VH - TPM Timer Channel 1 Value Register High; 0x00000049 ***/
union {
byte Byte;
} TPMC1VHSTR;
#define TPMC1VH _TPMC1V.Overlap_STR.TPMC1VHSTR.Byte
/*** TPMC1VL - TPM Timer Channel 1 Value Register Low; 0x0000004A ***/
union {
byte Byte;
} TPMC1VLSTR;
#define TPMC1VL _TPMC1V.Overlap_STR.TPMC1VLSTR.Byte
} Overlap_STR;
} TPMC1VSTR;
extern volatile TPMC1VSTR _TPMC1V @0x00000049;
#define TPMC1V _TPMC1V.Word
/*** SRS - System Reset Status Register; 0x00001800 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte LVD :1; /* Low Voltage Detect */
byte :1;
byte ILAD :1; /* Illegal Address */
byte ILOP :1; /* Illegal Opcode */
byte COP :1; /* Computer Operating Properly (COP) Watchdog */
byte PIN :1; /* External Reset Pin */
byte POR :1; /* Power-On Reset */
} Bits;
} SRSSTR;
extern volatile SRSSTR _SRS @0x00001800;
#define SRS _SRS.Byte
#define SRS_LVD _SRS.Bits.LVD
#define SRS_ILAD _SRS.Bits.ILAD
#define SRS_ILOP _SRS.Bits.ILOP
#define SRS_COP _SRS.Bits.COP
#define SRS_PIN _SRS.Bits.PIN
#define SRS_POR _SRS.Bits.POR
#define SRS_LVD_MASK 0x02
#define SRS_ILAD_MASK 0x08
#define SRS_ILOP_MASK 0x10
#define SRS_COP_MASK 0x20
#define SRS_PIN_MASK 0x40
#define SRS_POR_MASK 0x80
/*** SBDFR - System Background Debug Force Reset Register; 0x00001801 ***/
typedef union {
byte Byte;
struct {
byte BDFR :1; /* Background Debug Force Reset */
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
} Bits;
} SBDFRSTR;
extern volatile SBDFRSTR _SBDFR @0x00001801;
#define SBDFR _SBDFR.Byte
#define SBDFR_BDFR _SBDFR.Bits.BDFR
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