📄 io_map.h
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#define APCTL1_ADPC3 _APCTL1.Bits.ADPC3
#define APCTL1_ADPC _APCTL1.MergedBits.grpADPC
#define APCTL1_ADPC0_MASK 0x01
#define APCTL1_ADPC1_MASK 0x02
#define APCTL1_ADPC2_MASK 0x04
#define APCTL1_ADPC3_MASK 0x08
#define APCTL1_ADPC_MASK 0x0F
#define APCTL1_ADPC_BITNUM 0x00
/*** TPM2SC - TPM2 Timer Status and Control Register; 0x00000020 ***/
typedef union {
byte Byte;
struct {
byte PS0 :1; /* Prescale Divisor Select Bit 0 */
byte PS1 :1; /* Prescale Divisor Select Bit 1 */
byte PS2 :1; /* Prescale Divisor Select Bit 2 */
byte CLKSA :1; /* Clock Source Select A */
byte CLKSB :1; /* Clock Source Select B */
byte CPWMS :1; /* Center-Aligned PWM Select */
byte TOIE :1; /* Timer Overflow Interrupt Enable */
byte TOF :1; /* Timer Overflow Flag */
} Bits;
struct {
byte grpPS :3;
byte grpCLKSx :2;
byte :1;
byte :1;
byte :1;
} MergedBits;
} TPM2SCSTR;
extern volatile TPM2SCSTR _TPM2SC @0x00000020;
#define TPM2SC _TPM2SC.Byte
#define TPM2SC_PS0 _TPM2SC.Bits.PS0
#define TPM2SC_PS1 _TPM2SC.Bits.PS1
#define TPM2SC_PS2 _TPM2SC.Bits.PS2
#define TPM2SC_CLKSA _TPM2SC.Bits.CLKSA
#define TPM2SC_CLKSB _TPM2SC.Bits.CLKSB
#define TPM2SC_CPWMS _TPM2SC.Bits.CPWMS
#define TPM2SC_TOIE _TPM2SC.Bits.TOIE
#define TPM2SC_TOF _TPM2SC.Bits.TOF
#define TPM2SC_PS _TPM2SC.MergedBits.grpPS
#define TPM2SC_CLKSx _TPM2SC.MergedBits.grpCLKSx
#define TPM2SC_PS0_MASK 0x01
#define TPM2SC_PS1_MASK 0x02
#define TPM2SC_PS2_MASK 0x04
#define TPM2SC_CLKSA_MASK 0x08
#define TPM2SC_CLKSB_MASK 0x10
#define TPM2SC_CPWMS_MASK 0x20
#define TPM2SC_TOIE_MASK 0x40
#define TPM2SC_TOF_MASK 0x80
#define TPM2SC_PS_MASK 0x07
#define TPM2SC_PS_BITNUM 0x00
#define TPM2SC_CLKSx_MASK 0x18
#define TPM2SC_CLKSx_BITNUM 0x03
/*** TPM2CNT - TPM2 Counter Register; 0x00000021 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** TPM2CNTH - TPM2 Counter Register High; 0x00000021 ***/
union {
byte Byte;
} TPM2CNTHSTR;
#define TPM2CNTH _TPM2CNT.Overlap_STR.TPM2CNTHSTR.Byte
/*** TPM2CNTL - TPM2 Counter Register Low; 0x00000022 ***/
union {
byte Byte;
} TPM2CNTLSTR;
#define TPM2CNTL _TPM2CNT.Overlap_STR.TPM2CNTLSTR.Byte
} Overlap_STR;
} TPM2CNTSTR;
extern volatile TPM2CNTSTR _TPM2CNT @0x00000021;
#define TPM2CNT _TPM2CNT.Word
/*** TPM2MOD - TPM2 Timer Counter Modulo Register; 0x00000023 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** TPM2MODH - TPM2 Timer Counter Modulo Register High; 0x00000023 ***/
union {
byte Byte;
} TPM2MODHSTR;
#define TPM2MODH _TPM2MOD.Overlap_STR.TPM2MODHSTR.Byte
/*** TPM2MODL - TPM2 Timer Counter Modulo Register Low; 0x00000024 ***/
union {
byte Byte;
} TPM2MODLSTR;
#define TPM2MODL _TPM2MOD.Overlap_STR.TPM2MODLSTR.Byte
} Overlap_STR;
} TPM2MODSTR;
extern volatile TPM2MODSTR _TPM2MOD @0x00000023;
#define TPM2MOD _TPM2MOD.Word
/*** TPM2C0SC - TPM2 Timer Channel 0 Status and Control Register; 0x00000025 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte ELS0A :1; /* Edge/Level Select Bit A */
byte ELS0B :1; /* Edge/Level Select Bit B */
byte MS0A :1; /* Mode Select A for TPM Channel 0 */
byte MS0B :1; /* Mode Select B for TPM Channel 0 */
byte CH0IE :1; /* Channel 0 Interrupt Enable */
byte CH0F :1; /* Channel 0 Flag */
} Bits;
struct {
byte :1;
byte :1;
byte grpELS0x :2;
byte grpMS0x :2;
byte :1;
byte :1;
} MergedBits;
} TPM2C0SCSTR;
extern volatile TPM2C0SCSTR _TPM2C0SC @0x00000025;
#define TPM2C0SC _TPM2C0SC.Byte
#define TPM2C0SC_ELS0A _TPM2C0SC.Bits.ELS0A
#define TPM2C0SC_ELS0B _TPM2C0SC.Bits.ELS0B
#define TPM2C0SC_MS0A _TPM2C0SC.Bits.MS0A
#define TPM2C0SC_MS0B _TPM2C0SC.Bits.MS0B
#define TPM2C0SC_CH0IE _TPM2C0SC.Bits.CH0IE
#define TPM2C0SC_CH0F _TPM2C0SC.Bits.CH0F
#define TPM2C0SC_ELS0x _TPM2C0SC.MergedBits.grpELS0x
#define TPM2C0SC_MS0x _TPM2C0SC.MergedBits.grpMS0x
#define TPM2C0SC_ELS0A_MASK 0x04
#define TPM2C0SC_ELS0B_MASK 0x08
#define TPM2C0SC_MS0A_MASK 0x10
#define TPM2C0SC_MS0B_MASK 0x20
#define TPM2C0SC_CH0IE_MASK 0x40
#define TPM2C0SC_CH0F_MASK 0x80
#define TPM2C0SC_ELS0x_MASK 0x0C
#define TPM2C0SC_ELS0x_BITNUM 0x02
#define TPM2C0SC_MS0x_MASK 0x30
#define TPM2C0SC_MS0x_BITNUM 0x04
/*** TPM2C0V - TPM2 Timer Channel 0 Value Register; 0x00000026 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** TPM2C0VH - TPM2 Timer Channel 0 Value Register High; 0x00000026 ***/
union {
byte Byte;
} TPM2C0VHSTR;
#define TPM2C0VH _TPM2C0V.Overlap_STR.TPM2C0VHSTR.Byte
/*** TPM2C0VL - TPM2 Timer Channel 0 Value Register Low; 0x00000027 ***/
union {
byte Byte;
} TPM2C0VLSTR;
#define TPM2C0VL _TPM2C0V.Overlap_STR.TPM2C0VLSTR.Byte
} Overlap_STR;
} TPM2C0VSTR;
extern volatile TPM2C0VSTR _TPM2C0V @0x00000026;
#define TPM2C0V _TPM2C0V.Word
/*** ICSC1 - ICS Control Register 1; 0x00000038 ***/
typedef union {
byte Byte;
struct {
byte IREFSTEN :1; /* Internal Reference Stop Enable */
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte CLKS :1; /* Clock Source Select */
byte :1;
} Bits;
} ICSC1STR;
extern volatile ICSC1STR _ICSC1 @0x00000038;
#define ICSC1 _ICSC1.Byte
#define ICSC1_IREFSTEN _ICSC1.Bits.IREFSTEN
#define ICSC1_CLKS _ICSC1.Bits.CLKS
#define ICSC1_IREFSTEN_MASK 0x01
#define ICSC1_CLKS_MASK 0x40
/*** ICSC2 - ICS Control Register 2; 0x00000039 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte :1;
byte LP :1; /* Low Power Select */
byte :1;
byte :1;
byte BDIV0 :1; /* Bus Frequency Divider, bit 0 */
byte BDIV1 :1; /* Bus Frequency Divider, bit 1 */
} Bits;
struct {
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte grpBDIV :2;
} MergedBits;
} ICSC2STR;
extern volatile ICSC2STR _ICSC2 @0x00000039;
#define ICSC2 _ICSC2.Byte
#define ICSC2_LP _ICSC2.Bits.LP
#define ICSC2_BDIV0 _ICSC2.Bits.BDIV0
#define ICSC2_BDIV1 _ICSC2.Bits.BDIV1
#define ICSC2_BDIV _ICSC2.MergedBits.grpBDIV
#define ICSC2_LP_MASK 0x08
#define ICSC2_BDIV0_MASK 0x40
#define ICSC2_BDIV1_MASK 0x80
#define ICSC2_BDIV_MASK 0xC0
#define ICSC2_BDIV_BITNUM 0x06
/*** ICSTRM - ICS Trim Register; 0x0000003A ***/
typedef union {
byte Byte;
struct {
byte TRIM0 :1; /* ICS Trim Setting, bit 0 */
byte TRIM1 :1; /* ICS Trim Setting, bit 1 */
byte TRIM2 :1; /* ICS Trim Setting, bit 2 */
byte TRIM3 :1; /* ICS Trim Setting, bit 3 */
byte TRIM4 :1; /* ICS Trim Setting, bit 4 */
byte TRIM5 :1; /* ICS Trim Setting, bit 5 */
byte TRIM6 :1; /* ICS Trim Setting, bit 6 */
byte TRIM7 :1; /* ICS Trim Setting, bit 7 */
} Bits;
} ICSTRMSTR;
extern volatile ICSTRMSTR _ICSTRM @0x0000003A;
#define ICSTRM _ICSTRM.Byte
#define ICSTRM_TRIM0 _ICSTRM.Bits.TRIM0
#define ICSTRM_TRIM1 _ICSTRM.Bits.TRIM1
#define ICSTRM_TRIM2 _ICSTRM.Bits.TRIM2
#define ICSTRM_TRIM3 _ICSTRM.Bits.TRIM3
#define ICSTRM_TRIM4 _ICSTRM.Bits.TRIM4
#define ICSTRM_TRIM5 _ICSTRM.Bits.TRIM5
#define ICSTRM_TRIM6 _ICSTRM.Bits.TRIM6
#define ICSTRM_TRIM7 _ICSTRM.Bits.TRIM7
#define ICSTRM_TRIM0_MASK 0x01
#define ICSTRM_TRIM1_MASK 0x02
#define ICSTRM_TRIM2_MASK 0x04
#define ICSTRM_TRIM3_MASK 0x08
#define ICSTRM_TRIM4_MASK 0x10
#define ICSTRM_TRIM5_MASK 0x20
#define ICSTRM_TRIM6_MASK 0x40
#define ICSTRM_TRIM7_MASK 0x80
/*** ICSSC - ICS Status and Control; 0x0000003B ***/
typedef union {
byte Byte;
struct {
byte FTRIM :1; /* ICS Fine Trim */
byte :1;
byte CLKST :1; /* Clock Mode Status */
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
} Bits;
} ICSSCSTR;
extern volatile ICSSCSTR _ICSSC @0x0000003B;
#define ICSSC _ICSSC.Byte
#define ICSSC_FTRIM _ICSSC.Bits.FTRIM
#define ICSSC_CLKST _ICSSC.Bits.CLKST
#define ICSSC_FTRIM_MASK 0x01
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