hw_config.c

STM32的低功耗例程

/******************** (C) COPYRIGHT 2007 STMicroelectronics ********************
* File Name          : hw_config.c
* Author             : MCD Application Team
* Version            : V1.0
* Date               : 10/10/2007
* Description        : Hardware configuration file.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/

/* Includes ------------------------------------------------------------------*/
#include "stm32f10x_lib.h"
#include "hw_config.h"

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
ErrorStatus HSEStartUpStatus;

/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/

/*******************************************************************************
* Function Name  : RCC_Configuration
* Description    : Configures the different system clocks.
* Input          : None
* Output         : None
* Return         : None
*******************************************************************************/
void RCC_Configuration(void)
{
  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/   
  /* RCC system reset(for debug purpose) */
  RCC_DeInit();


#ifdef HSE_PLL_ON
  /* Enable HSE */
  RCC_HSEConfig(RCC_HSE_ON);

  /* Wait till HSE is ready */
  HSEStartUpStatus = RCC_WaitForHSEStartUp();
  
  if(HSEStartUpStatus == SUCCESS)
  {
    /* Enable Prefetch Buffer */
    FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
    
    /* Set the Flash wait states */
    #ifdef HSE_PLL_ON_72MHz /* 2 wait states */
    FLASH_SetLatency(FLASH_Latency_2);
    #endif
    
    #ifdef HSE_PLL_ON_48MHz /* 1 wait state */ 
    FLASH_SetLatency(FLASH_Latency_1);
    #endif
    
    #ifdef HSE_PLL_ON_36MHz /* 1 wait state */
    FLASH_SetLatency(FLASH_Latency_1);
    #endif
    
    #ifdef HSE_PLL_ON_24MHz /* 0 wait state */
    FLASH_SetLatency(FLASH_Latency_0);
    #endif
    
    #ifdef HSE_PLL_ON_16MHz /* 0 wait state */
    FLASH_SetLatency(FLASH_Latency_0);
    #endif
    
    /* HCLK = SYSCLK */
    RCC_HCLKConfig(RCC_SYSCLK_Div1); 
  
    /* PCLK2 = HCLK/2 */
    RCC_PCLK2Config(RCC_HCLK_Div2); 

    /* PCLK1 = HCLK/4 */
    RCC_PCLK1Config(RCC_HCLK_Div4);

    #ifdef HSE_PLL_ON_72MHz
    /* PLLCLK = 8MHz * 9 = 72 MHz */
    RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
    #endif
    
    #ifdef HSE_PLL_ON_48MHz
    /* PLLCLK = 8MHz * 6 = 48 MHz */
    RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_6);
    #endif
    
    #ifdef HSE_PLL_ON_36MHz
    /* PLLCLK = 8MHz / 2 * 9 = 36 MHz */
    RCC_PLLConfig(RCC_PLLSource_HSE_Div2, RCC_PLLMul_9);
    #endif
    
    #ifdef HSE_PLL_ON_24MHz
    /* PLLCLK = 8MHz * 3 = 24 MHz */
    RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_3);
    #endif
    
    #ifdef HSE_PLL_ON_16MHz
    /* PLLCLK = 8MHz * 2 = 16 MHz */
    RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_2);
    #endif
    
    /* Enable PLL */ 
    RCC_PLLCmd(ENABLE);

    /* Wait till PLL is ready */
    while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
    {
    }

    /* Select PLL as system clock source */
    RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);

    /* Wait till PLL is used as system clock source */
    while(RCC_GetSYSCLKSource() != 0x08)
    {
    }
  }
#endif /* HSE_PLL_ON */
    
#ifdef HSE_PLL_OFF
  
  /* Enable HSE */
  RCC_HSEConfig(RCC_HSE_ON);

  /* Wait till HSE is ready */
  HSEStartUpStatus = RCC_WaitForHSEStartUp();
  
 if(HSEStartUpStatus == SUCCESS)
  {
    /* Disable Prefetch Buffer */
    FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Disable);
  
    /* Flash 0 wait state */
    FLASH_SetLatency(FLASH_Latency_0);
    
    #ifdef HSE_PLL_OFF_8MHz
    /* HCLK = SYSCLK */
    RCC_HCLKConfig(RCC_SYSCLK_Div1); 
    #endif 

    #ifdef HSE_PLL_OFF_4MHz
    /* HCLK = SYSCLK/2 = 4MHz */
    RCC_HCLKConfig(RCC_SYSCLK_Div2); 
    #endif 
    
    #ifdef HSE_PLL_OFF_2MHz
    /* HCLK = SYSCLK/4 = 2MHz */
    RCC_HCLKConfig(RCC_SYSCLK_Div4); 
    #endif 
    
    #ifdef HSE_PLL_OFF_1MHz
    /* HCLK = SYSCLK/8 = 1MHz */
    RCC_HCLKConfig(RCC_SYSCLK_Div8); 
    #endif 
    
    #ifdef HSE_PLL_OFF_500KHz
    /* HCLK = SYSCLK/16 = 500KHz */
    RCC_HCLKConfig(RCC_SYSCLK_Div16); 
    #endif 
    
    #ifdef HSE_PLL_OFF_125KHz
    /* HCLK = SYSCLK/64 = 125KHz */
    RCC_HCLKConfig(RCC_SYSCLK_Div64); 
    #endif 
    
    /* PCLK2 = HCLK/2 */
    RCC_PCLK2Config(RCC_HCLK_Div2); 

    /* PCLK1 = HCLK/4 */
    RCC_PCLK1Config(RCC_HCLK_Div4);
  
    /* Select HSE as system clock source */
    RCC_SYSCLKConfig(RCC_SYSCLKSource_HSE);

    /* Wait till HSE is used as system clock source */
    while(RCC_GetSYSCLKSource() != 0x04)
    {
    }  
  }
#endif /* HSE_PLL_OFF */ 
 
 
#ifdef HSI_PLL_ON
 
  /* Enable Prefetch Buffer */
  FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
 
  /* Set the Flash wait states */
  #ifdef HSI_PLL_ON_64MHz /* 2 wait states */
  FLASH_SetLatency(FLASH_Latency_2);
  #endif
    
  #ifdef HSI_PLL_ON_48MHz /* 1 wait state */ 
  FLASH_SetLatency(FLASH_Latency_1);
  #endif
    
  #ifdef HSI_PLL_ON_36MHz /* 1 wait state */
  FLASH_SetLatency(FLASH_Latency_1);
  #endif
    
  #ifdef HSI_PLL_ON_24MHz /* 0 wait state */
  FLASH_SetLatency(FLASH_Latency_0);
  #endif
    
  #ifdef HSI_PLL_ON_16MHz /* 0 wait state */
  FLASH_SetLatency(FLASH_Latency_0);
  #endif
    
  /* HCLK = SYSCLK */
  RCC_HCLKConfig(RCC_SYSCLK_Div1); 
  
  /* PCLK2 = HCLK/2 */
  RCC_PCLK2Config(RCC_HCLK_Div2); 

  /* PCLK1 = HCLK/4 */
  RCC_PCLK1Config(RCC_HCLK_Div4);  
  
  #ifdef HSI_PLL_ON_64MHz
  /* PLLCLK = 8MHz/2 * 16 = 64 MHz */
  RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_16);
  #endif
    
  #ifdef HSI_PLL_ON_48MHz
  /* PLLCLK = 8MHz/2 * 12 = 48 MHz */
  RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_12);
  #endif
    
  #ifdef HSI_PLL_ON_36MHz
  /* PLLCLK = 8MHz/2 * 9 = 36 MHz */
  RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_9);
  #endif
    
  #ifdef HSI_PLL_ON_24MHz
  /* PLLCLK = 8MHz/2 * 6 = 24 MHz */
  RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_6);
  #endif
    
  #ifdef HSI_PLL_ON_16MHz
  /* PLLCLK = 8MHz/2 * 4 = 16 MHz */
  RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_4);
  #endif
    
  /* Enable PLL */ 
  RCC_PLLCmd(ENABLE);

  /* Wait till PLL is ready */
  while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
  {
  }

  /* Select PLL as system clock source */
  RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);