📄 at45db161.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.0 [Build 951] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o.\output\at45db161.o --device=DARMST --apcs=interwork -O0 -Id:\Keil\ARM\INC\ST\71x src\BSP\AT45DB161.C]
ARM
AREA ||.text.7||, CODE, READONLY, ALIGN=2
AT45Delay PROC
;;;38 {
;;;39 while ( n-- )
000000 e1a00000 MOV r0,r0
|L1.4|
000004 e1b01000 MOVS r1,r0
000008 e2400001 SUB r0,r0,#1
00000c 1afffffc BNE |L1.4|
;;;40 ;
;;;41 }
000010 e12fff1e BX lr
ENDP
initAT45DB161 PROC
;;;52 void initAT45DB161(void)
;;;53 {
000014 e92d4010 PUSH {r4,lr}
;;;54
;;;55 GPIO_Config (GPIO0, BSPI1_SO | BSPI1_SI | BSPI1_SCLK, GPIO_AF_PP);
000018 e3a02007 MOV r2,#7
00001c e3a01070 MOV r1,#0x70
000020 e59f02ec LDR r0,|L1.788|
000024 ebfffffe BL GPIO_Config
;;;56 GPIO_Config (GPIO1, AT45_CS, GPIO_OUT_PP);
000028 e3a02005 MOV r2,#5
00002c e3a01002 MOV r1,#2
000030 e59f02e0 LDR r0,|L1.792|
000034 ebfffffe BL GPIO_Config
;;;57 GPIO_Config (GPIO0, BSPI1_SSN, GPIO_IN_TRI_CMOS);
000038 e3a02002 MOV r2,#2
00003c e3a01080 MOV r1,#0x80
000040 e59f02cc LDR r0,|L1.788|
000044 ebfffffe BL GPIO_Config
;;;58 AT45_Chip_Select_DISABLE;
000048 e59f02c8 LDR r0,|L1.792|
00004c e1d000bc LDRH r0,[r0,#0xc]
000050 e3800002 ORR r0,r0,#2
000054 e59f12bc LDR r1,|L1.792|
000058 e1c100bc STRH r0,[r1,#0xc]
;;;59 /* -------------------------------------------
;;;60 Configue BSPI1 as a Master
;;;61 ------------------------------------------- */
;;;62 /* Initialize BSPI1 */
;;;63 BSPI_Init ( BSPI1 ) ;
00005c e59f02b8 LDR r0,|L1.796|
000060 ebfffffe BL BSPI_Init
;;;64 BSPI_ClockDividerConfig ( BSPI1, 6); // Configure Baud rate Frequency :-->APB1/8
000064 e1a00000 MOV r0,r0
000068 e3a00006 MOV r0,#6
00006c e59f12a8 LDR r1,|L1.796|
000070 e1c101b0 STRH r0,[r1,#0x10]
000074 e1a00000 MOV r0,r0
;;;65 BSPI_Enable ( BSPI1, ENABLE ); //Enable BSPI1 */
000078 e1a00000 MOV r0,r0
00007c e3a00001 MOV r0,#1
000080 e3500001 CMP r0,#1
000084 1a000004 BNE |L1.156|
000088 e1c10000 BIC r0,r1,r0
00008c e1d000b8 LDRH r0,[r0,#8]
000090 e3800001 ORR r0,r0,#1
000094 e1c100b8 STRH r0,[r1,#8]
000098 ea000004 B |L1.176|
|L1.156|
00009c e59f0278 LDR r0,|L1.796|
0000a0 e1d000b8 LDRH r0,[r0,#8]
0000a4 e3c00001 BIC r0,r0,#1
0000a8 e59f126c LDR r1,|L1.796|
0000ac e1c100b8 STRH r0,[r1,#8]
|L1.176|
0000b0 e1a00000 MOV r0,r0
0000b4 e1a00000 MOV r0,r0
;;;66 BSPI_MasterEnable ( BSPI1, ENABLE);//Configure BSPI0 as a Master */
0000b8 e1a00000 MOV r0,r0
0000bc e3a00001 MOV r0,#1
0000c0 e3500001 CMP r0,#1
0000c4 1a000005 BNE |L1.224|
0000c8 e59f024c LDR r0,|L1.796|
0000cc e1d000b8 LDRH r0,[r0,#8]
0000d0 e3800002 ORR r0,r0,#2
0000d4 e59f1240 LDR r1,|L1.796|
0000d8 e1c100b8 STRH r0,[r1,#8]
0000dc ea000004 B |L1.244|
|L1.224|
0000e0 e59f0234 LDR r0,|L1.796|
0000e4 e1d000b8 LDRH r0,[r0,#8]
0000e8 e3c00002 BIC r0,r0,#2
0000ec e59f1228 LDR r1,|L1.796|
0000f0 e1c100b8 STRH r0,[r1,#8]
|L1.244|
0000f4 e1a00000 MOV r0,r0
0000f8 e1a00000 MOV r0,r0
;;;67 BSPI_ClkActiveHigh( BSPI1, DISABLE);//Configure the clock to be active high */
0000fc e1a00000 MOV r0,r0
000100 e3a00000 MOV r0,#0
000104 e3500001 CMP r0,#1
000108 1a000005 BNE |L1.292|
00010c e59f0208 LDR r0,|L1.796|
000110 e1d000b8 LDRH r0,[r0,#8]
000114 e3800c01 ORR r0,r0,#0x100
000118 e59f11fc LDR r1,|L1.796|
00011c e1c100b8 STRH r0,[r1,#8]
000120 ea000004 B |L1.312|
|L1.292|
000124 e59f01f0 LDR r0,|L1.796|
000128 e1d000b8 LDRH r0,[r0,#8]
00012c e3c00c01 BIC r0,r0,#0x100
000130 e59f11e4 LDR r1,|L1.796|
000134 e1c100b8 STRH r0,[r1,#8]
|L1.312|
000138 e1a00000 MOV r0,r0
00013c e1a00000 MOV r0,r0
;;;68 BSPI_ClkFEdge( BSPI1, DISABLE); //Enable capturing the first Data sample on the first edge of SCK */
000140 e1a00000 MOV r0,r0
000144 e3a00000 MOV r0,#0
000148 e3500001 CMP r0,#1
00014c 1a000005 BNE |L1.360|
000150 e59f01c4 LDR r0,|L1.796|
000154 e1d000b8 LDRH r0,[r0,#8]
000158 e3800c02 ORR r0,r0,#0x200
00015c e59f11b8 LDR r1,|L1.796|
000160 e1c100b8 STRH r0,[r1,#8]
000164 ea000004 B |L1.380|
|L1.360|
000168 e59f01ac LDR r0,|L1.796|
00016c e1d000b8 LDRH r0,[r0,#8]
000170 e3c00c02 BIC r0,r0,#0x200
000174 e59f11a0 LDR r1,|L1.796|
000178 e1c100b8 STRH r0,[r1,#8]
|L1.380|
00017c e1a00000 MOV r0,r0
000180 e1a00000 MOV r0,r0
;;;69 BSPI_8bLEn( BSPI1, ENABLE); //Set the word length to 8 bit */
000184 e1a00000 MOV r0,r0
000188 e3a00001 MOV r0,#1
00018c e3500000 CMP r0,#0
000190 1a000005 BNE |L1.428|
000194 e59f0180 LDR r0,|L1.796|
000198 e1d000b8 LDRH r0,[r0,#8]
00019c e3800b01 ORR r0,r0,#0x400
0001a0 e59f1174 LDR r1,|L1.796|
0001a4 e1c100b8 STRH r0,[r1,#8]
0001a8 ea000004 B |L1.448|
|L1.428|
0001ac e59f0168 LDR r0,|L1.796|
0001b0 e1d000b8 LDRH r0,[r0,#8]
0001b4 e3c00b03 BIC r0,r0,#0xc00
0001b8 e59f115c LDR r1,|L1.796|
0001bc e1c100b8 STRH r0,[r1,#8]
|L1.448|
0001c0 e1a00000 MOV r0,r0
0001c4 e1a00000 MOV r0,r0
;;;70 // BSPI_TrFifoDepth(BSPI1, 1); //Set tx fifo 1 word
;;;71 // BSPI_RcFifoDepth(BSPI1, 1); //Set rx fifo 1 word
;;;72 }
0001c8 e8bd4010 POP {r4,lr}
0001cc e12fff1e BX lr
ENDP
BPSI_DataSendReceive PROC
;;;84 u8 BPSI_DataSendReceive(u8 data)
;;;85 {
0001d0 e1a01000 MOV r1,r0
;;;86 u8 temp;
;;;87 while(BSPI1->CSR2&BSPI_RFNE)
0001d4 ea000002 B |L1.484|
;;;88 temp = BSPI1->RXR;
|L1.472|
0001d8 e59f213c LDR r2,|L1.796|
0001dc e1d220b0 LDRH r2,[r2,#0]
0001e0 e20200ff AND r0,r2,#0xff
|L1.484|
0001e4 e59f2130 LDR r2,|L1.796| ;87
0001e8 e1d220bc LDRH r2,[r2,#0xc] ;87
0001ec e3120008 TST r2,#8 ;87
0001f0 1afffff8 BNE |L1.472| ;87
;;;89 while(!(BSPI1->CSR2&BSPI_TFE)); /* Wait until the Transmit FIFO is empty */
0001f4 e1a00000 MOV r0,r0
|L1.504|
0001f8 e59f211c LDR r2,|L1.796|
0001fc e1d220bc LDRH r2,[r2,#0xc]
000200 e3120040 TST r2,#0x40
000204 0afffffb BEQ |L1.504|
;;;90 BSPI1->TXR = data<<8; /* Send data to Transmit buffer */
000208 e59f2110 LDR r2,|L1.800|
00020c e0022401 AND r2,r2,r1,LSL #8
000210 e59f3104 LDR r3,|L1.796|
000214 e1c320b4 STRH r2,[r3,#4]
;;;91 while(!(BSPI1->CSR2&BSPI_RFF)); /* Wait until the end of transmission */
000218 e1a00000 MOV r0,r0
|L1.540|
00021c e59f20f8 LDR r2,|L1.796|
000220 e1d220bc LDRH r2,[r2,#0xc]
000224 e3120010 TST r2,#0x10
000228 0afffffb BEQ |L1.540|
;;;92 temp = (BSPI1->RXR)>>8; /* Read the received data */
00022c e59f20e8 LDR r2,|L1.796|
000230 e1d220b0 LDRH r2,[r2,#0]
000234 e1a00442 ASR r0,r2,#8
;;;93 return temp;
;;;94 }
000238 e12fff1e BX lr
ENDP
AT45_Reset PROC
;;;106 void AT45_Reset(void)
;;;107 {
00023c e92d4010 PUSH {r4,lr}
;;;108 AT45_Chip_Select_DISABLE;
000240 e59f00d0 LDR r0,|L1.792|
000244 e1d000bc LDRH r0,[r0,#0xc]
000248 e3800002 ORR r0,r0,#2
00024c e59f10c4 LDR r1,|L1.792|
000250 e1c100bc STRH r0,[r1,#0xc]
;;;109 os_dly_wait (8);
000254 e3a00008 MOV r0,#8
000258 ebfffffe BL os_dly_wait
;;;110 AT45_Chip_Select_ENABLE; //select dataflash
00025c e59f00b4 LDR r0,|L1.792|
000260 e1d000bc LDRH r0,[r0,#0xc]
000264 e3c00002 BIC r0,r0,#2
000268 e59f10a8 LDR r1,|L1.792|
00026c e1c100bc STRH r0,[r1,#0xc]
;;;111 }
000270 e8bd4010 POP {r4,lr}
000274 e12fff1e BX lr
ENDP
AT45_Read_REG PROC
;;;113 u8 AT45_Read_REG(u8 reg)
;;;114 {
000278 e92d4030 PUSH {r4,r5,lr}
00027c e1a04000 MOV r4,r0
;;;115 u8 tmp;
;;;116 AT45_Chip_Select_ENABLE;
000280 e59f0090 LDR r0,|L1.792|
000284 e1d000bc LDRH r0,[r0,#0xc]
000288 e3c00002 BIC r0,r0,#2
00028c e59f1084 LDR r1,|L1.792|
000290 e1c100bc STRH r0,[r1,#0xc]
;;;117 BPSI_DataSendReceive(reg);
000294 e1a00004 MOV r0,r4
000298 ebfffffe BL BPSI_DataSendReceive
;;;118 tmp = BPSI_DataSendReceive(0x0);
00029c e3a00000 MOV r0,#0
0002a0 ebfffffe BL BPSI_DataSendReceive
0002a4 e1a05000 MOV r5,r0
;;;119 AT45_Chip_Select_DISABLE;
0002a8 e59f0068 LDR r0,|L1.792|
0002ac e1d000bc LDRH r0,[r0,#0xc]
0002b0 e3800002 ORR r0,r0,#2
0002b4 e59f105c LDR r1,|L1.792|
0002b8 e1c100bc STRH r0,[r1,#0xc]
;;;120
;;;121 return tmp;
0002bc e1a00005 MOV r0,r5
0002c0 e8bd4030 POP {r4,r5,lr}
;;;122 }
0002c4 e12fff1e BX lr
ENDP
AT45_Ready PROC
;;;134 void AT45_Ready(void)
;;;135 {
0002c8 e92d4010 PUSH {r4,lr}
;;;136 u8 tmp = 0x00;
0002cc e3a04000 MOV r4,#0
;;;137
;;;138 while(!(tmp & 0x80))
0002d0 ea000002 B |L1.736|
;;;139 {
;;;140 tmp = AT45_Read_REG(0xd7);
|L1.724|
0002d4 e3a000d7 MOV r0,#0xd7
0002d8 ebfffffe BL AT45_Read_REG
0002dc e1a04000 MOV r4,r0
|L1.736|
0002e0 e3140080 TST r4,#0x80 ;138
0002e4 0afffffa BEQ |L1.724| ;138
;;;141 }
;;;142 }
0002e8 e8bd4010 POP {r4,lr}
0002ec e12fff1e BX lr
ENDP
Detect_AT45DB PROC
;;;153 u8 Detect_AT45DB(void)
;;;154 {
0002f0 e92d4010 PUSH {r4,lr}
;;;155 u8 temp;
;;;156
;;;157 AT45_Ready(); //wait until dataflash is ready
0002f4 ebfffffe BL AT45_Ready
;;;158 temp = AT45_Read_REG(0xD7);
0002f8 e3a000d7 MOV r0,#0xd7
0002fc ebfffffe BL AT45_Read_REG
000300 e1a04000 MOV r4,r0
;;;159
;;;160 return (temp>>2)&0x0f;
000304 e3a0000f MOV r0,#0xf
000308 e0000144 AND r0,r0,r4,ASR #2
00030c e8bd4010 POP {r4,lr}
;;;161 }
000310 e12fff1e BX lr
|L1.788|
000314 e0003000 DCD 0xe0003000
|L1.792|
000318 e0004000 DCD 0xe0004000
|L1.796|
00031c c000b000 DCD 0xc000b000
|L1.800|
000320 0000ffff DCD 0x0000ffff
ENDP
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