📄 at45db161.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.0 [Build 951] for uVision
; commandline ArmCC [--thumb --debug -c --asm --interleave -o.\output\at45db161.o --feedback=.\output\Testat45db161.fed --device=DARMST --apcs=interwork -O0 -Id:\Keil\ARM\INC\ST\71x src\BSP\AT45DB161.C]
THUMB
AREA ||.text.7||, CODE, READONLY, ALIGN=2
initAT45DB161 PROC
;;;57 void initAT45DB161(void)
;;;58 {
000000 b510 PUSH {r4,lr}
;;;59
;;;60 GPIO_Config (GPIO0, BSPI1_SO | BSPI1_SI | BSPI1_SCLK, GPIO_AF_PP);
000002 2207 MOVS r2,#7
000004 2170 MOVS r1,#0x70
000006 48ff LDR r0,|L1.1028|
000008 f7ff fffe BL GPIO_Config
;;;61 GPIO_Config (GPIO1, AT45_CS, GPIO_OUT_PP);
00000c 2205 MOVS r2,#5
00000e 2101 MOVS r1,#1
000010 03c9 LSLS r1,r1,#15
000012 48fd LDR r0,|L1.1032|
000014 f7ff fffe BL GPIO_Config
;;;62 GPIO_Config (GPIO0, BSPI1_SSN, GPIO_IN_TRI_CMOS);
000018 2202 MOVS r2,#2
00001a 2180 MOVS r1,#0x80
00001c 48f9 LDR r0,|L1.1028|
00001e f7ff fffe BL GPIO_Config
;;;63 AT45_Chip_Select_DISABLE;
000022 48f9 LDR r0,|L1.1032|
000024 8980 LDRH r0,[r0,#0xc]
000026 2101 MOVS r1,#1
000028 03c9 LSLS r1,r1,#15
00002a 4308 ORRS r0,r0,r1
00002c 49f6 LDR r1,|L1.1032|
00002e 8188 STRH r0,[r1,#0xc]
;;;64 /* -------------------------------------------
;;;65 Configue BSPI1 as a Master
;;;66 ------------------------------------------- */
;;;67 /* Initialize BSPI1 */
;;;68 BSPI_Init ( BSPI1 ) ;
000030 48f6 LDR r0,|L1.1036|
000032 f7ff fffe BL BSPI_Init
;;;69 BSPI_ClockDividerConfig ( BSPI1, 6); // Configure Baud rate Frequency :-->APB1/8
000036 46c0 MOV r8,r8
000038 2006 MOVS r0,#6
00003a 49f4 LDR r1,|L1.1036|
00003c 8208 STRH r0,[r1,#0x10]
00003e 46c0 MOV r8,r8
;;;70 BSPI_Enable ( BSPI1, ENABLE ); //Enable BSPI1 */
000040 46c0 MOV r8,r8
000042 2001 MOVS r0,#1
000044 2801 CMP r0,#1
000046 d106 BNE |L1.86|
000048 0008 MOVS r0,r1
00004a 8900 LDRH r0,[r0,#8]
00004c 2101 MOVS r1,#1
00004e 4308 ORRS r0,r0,r1
000050 49ee LDR r1,|L1.1036|
000052 8108 STRH r0,[r1,#8]
000054 e005 B |L1.98|
|L1.86|
000056 48ed LDR r0,|L1.1036|
000058 8900 LDRH r0,[r0,#8]
00005a 0840 LSRS r0,r0,#1
00005c 0040 LSLS r0,r0,#1
00005e 49eb LDR r1,|L1.1036|
000060 8108 STRH r0,[r1,#8]
|L1.98|
000062 46c0 MOV r8,r8
;;;71 BSPI_MasterEnable ( BSPI1, ENABLE);//Configure BSPI0 as a Master */
000064 46c0 MOV r8,r8
000066 2001 MOVS r0,#1
000068 2801 CMP r0,#1
00006a d106 BNE |L1.122|
00006c 48e7 LDR r0,|L1.1036|
00006e 8900 LDRH r0,[r0,#8]
000070 2102 MOVS r1,#2
000072 4308 ORRS r0,r0,r1
000074 49e5 LDR r1,|L1.1036|
000076 8108 STRH r0,[r1,#8]
000078 e005 B |L1.134|
|L1.122|
00007a 48e4 LDR r0,|L1.1036|
00007c 8900 LDRH r0,[r0,#8]
00007e 2102 MOVS r1,#2
000080 4388 BICS r0,r0,r1
000082 49e2 LDR r1,|L1.1036|
000084 8108 STRH r0,[r1,#8]
|L1.134|
000086 46c0 MOV r8,r8
;;;72 BSPI_ClkActiveHigh( BSPI1, DISABLE);//Configure the clock to be active high */
000088 46c0 MOV r8,r8
00008a 2000 MOVS r0,#0
00008c 2801 CMP r0,#1
00008e d107 BNE |L1.160|
000090 48de LDR r0,|L1.1036|
000092 8900 LDRH r0,[r0,#8]
000094 21ff MOVS r1,#0xff
000096 1c49 ADDS r1,r1,#1
000098 4308 ORRS r0,r0,r1
00009a 49dc LDR r1,|L1.1036|
00009c 8108 STRH r0,[r1,#8]
00009e e006 B |L1.174|
|L1.160|
0000a0 48da LDR r0,|L1.1036|
0000a2 8900 LDRH r0,[r0,#8]
0000a4 21ff MOVS r1,#0xff
0000a6 1c49 ADDS r1,r1,#1
0000a8 4388 BICS r0,r0,r1
0000aa 49d8 LDR r1,|L1.1036|
0000ac 8108 STRH r0,[r1,#8]
|L1.174|
0000ae 46c0 MOV r8,r8
;;;73 BSPI_ClkFEdge( BSPI1, DISABLE); //Enable capturing the first Data sample on the first edge of SCK */
0000b0 46c0 MOV r8,r8
0000b2 2000 MOVS r0,#0
0000b4 2801 CMP r0,#1
0000b6 d107 BNE |L1.200|
0000b8 48d4 LDR r0,|L1.1036|
0000ba 8900 LDRH r0,[r0,#8]
0000bc 2101 MOVS r1,#1
0000be 0249 LSLS r1,r1,#9
0000c0 4308 ORRS r0,r0,r1
0000c2 49d2 LDR r1,|L1.1036|
0000c4 8108 STRH r0,[r1,#8]
0000c6 e006 B |L1.214|
|L1.200|
0000c8 48d0 LDR r0,|L1.1036|
0000ca 8900 LDRH r0,[r0,#8]
0000cc 2101 MOVS r1,#1
0000ce 0249 LSLS r1,r1,#9
0000d0 4388 BICS r0,r0,r1
0000d2 49ce LDR r1,|L1.1036|
0000d4 8108 STRH r0,[r1,#8]
|L1.214|
0000d6 46c0 MOV r8,r8
;;;74 BSPI_8bLEn( BSPI1, ENABLE); //Set the word length to 8 bit */
0000d8 46c0 MOV r8,r8
0000da 2001 MOVS r0,#1
0000dc 2800 CMP r0,#0
0000de d107 BNE |L1.240|
0000e0 48ca LDR r0,|L1.1036|
0000e2 8900 LDRH r0,[r0,#8]
0000e4 2101 MOVS r1,#1
0000e6 0289 LSLS r1,r1,#10
0000e8 4308 ORRS r0,r0,r1
0000ea 49c8 LDR r1,|L1.1036|
0000ec 8108 STRH r0,[r1,#8]
0000ee e006 B |L1.254|
|L1.240|
0000f0 48c6 LDR r0,|L1.1036|
0000f2 8900 LDRH r0,[r0,#8]
0000f4 2103 MOVS r1,#3
0000f6 0289 LSLS r1,r1,#10
0000f8 4388 BICS r0,r0,r1
0000fa 49c4 LDR r1,|L1.1036|
0000fc 8108 STRH r0,[r1,#8]
|L1.254|
0000fe 46c0 MOV r8,r8
;;;75 // BSPI_TrFifoDepth(BSPI1, 1); //Set tx fifo 1 word
;;;76 // BSPI_RcFifoDepth(BSPI1, 1); //Set rx fifo 1 word
;;;77 }
000100 bc10 POP {r4}
000102 bc08 POP {r3}
000104 4718 BX r3
ENDP
BPSI_DataSendReceive PROC
;;;89 u8 BPSI_DataSendReceive(u8 data)
;;;90 {
000106 b410 PUSH {r4}
000108 0001 MOVS r1,r0
;;;91 u8 temp;
;;;92 u32 i;
;;;93 i = 1000000;
00010a 4bc1 LDR r3,|L1.1040|
;;;94 while ( BSPI1->CSR2 & BSPI_RFNE )
00010c e009 B |L1.290|
;;;95 {
;;;96 temp = BSPI1->RXR;
|L1.270|
00010e 48bf LDR r0,|L1.1036|
000110 8800 LDRH r0,[r0,#0]
000112 0602 LSLS r2,r0,#24
000114 0e12 LSRS r2,r2,#24
;;;97 SPI1_ERR_EXIT(i);
000116 1e5b SUBS r3,r3,#1
000118 2b00 CMP r3,#0
00011a d102 BNE |L1.290|
00011c 2000 MOVS r0,#0
;;;98 }
;;;99 while ( !( BSPI1->CSR2 & BSPI_TFE ) )
;;;100 {
;;;101 SPI1_ERR_EXIT(i);
;;;102 }
;;;103 BSPI1->TXR = data << 8;
;;;104 while ( !( BSPI1->CSR2 & BSPI_RFF ) )
;;;105 {
;;;106 SPI1_ERR_EXIT(i);
;;;107 }
;;;108
;;;109 temp = ( BSPI1->RXR >> 8 );
;;;110 return temp;
;;;111 }
|L1.286|
00011e bc10 POP {r4}
000120 4770 BX lr
|L1.290|
000122 48ba LDR r0,|L1.1036| ;94
000124 8980 LDRH r0,[r0,#0xc] ;94
000126 2408 MOVS r4,#8 ;94
000128 4220 TST r0,r4 ;94
00012a d1f0 BNE |L1.270| ;94
00012c e004 B |L1.312| ;99
|L1.302|
00012e 1e5b SUBS r3,r3,#1 ;101
000130 2b00 CMP r3,#0 ;101
000132 d101 BNE |L1.312| ;101
000134 2000 MOVS r0,#0 ;101
000136 e7f2 B |L1.286| ;101
|L1.312|
000138 48b4 LDR r0,|L1.1036| ;99
00013a 8980 LDRH r0,[r0,#0xc] ;99
00013c 2440 MOVS r4,#0x40 ;99
00013e 4220 TST r0,r4 ;99
000140 d0f5 BEQ |L1.302| ;99
000142 0208 LSLS r0,r1,#8 ;103
000144 4cb1 LDR r4,|L1.1036| ;103
000146 80a0 STRH r0,[r4,#4] ;103
000148 e004 B |L1.340| ;104
|L1.330|
00014a 1e5b SUBS r3,r3,#1 ;106
00014c 2b00 CMP r3,#0 ;106
00014e d101 BNE |L1.340| ;106
000150 2000 MOVS r0,#0 ;106
000152 e7e4 B |L1.286| ;106
|L1.340|
000154 48ad LDR r0,|L1.1036| ;104
000156 8980 LDRH r0,[r0,#0xc] ;104
000158 2410 MOVS r4,#0x10 ;104
00015a 4220 TST r0,r4 ;104
00015c d0f5 BEQ |L1.330| ;104
00015e 48ab LDR r0,|L1.1036| ;109
000160 8800 LDRH r0,[r0,#0] ;109
000162 1202 ASRS r2,r0,#8 ;109
000164 0010 MOVS r0,r2 ;110
000166 e7da B |L1.286| ;110
ENDP
AT45_Read_REG PROC
;;;130 u8 AT45_Read_REG(void)
;;;131 {
000168 b510 PUSH {r4,lr}
;;;132 u8 tmp;
;;;133 AT45_Chip_Select_ENABLE;
00016a 48a7 LDR r0,|L1.1032|
00016c 8980 LDRH r0,[r0,#0xc]
00016e 2101 MOVS r1,#1
000170 03c9 LSLS r1,r1,#15
000172 4388 BICS r0,r0,r1
000174 49a4 LDR r1,|L1.1032|
000176 8188 STRH r0,[r1,#0xc]
;;;134 BPSI_DataSendReceive(0xD7);
000178 20d7 MOVS r0,#0xd7
00017a f7ff fffe BL BPSI_DataSendReceive
;;;135 tmp = BPSI_DataSendReceive(0x0);
00017e 2000 MOVS r0,#0
000180 f7ff fffe BL BPSI_DataSendReceive
000184 0004 MOVS r4,r0
;;;136 AT45_Chip_Select_DISABLE;
000186 48a0 LDR r0,|L1.1032|
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