vectors.c

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/** ###################################################################
**     THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename  : Vectors.C
**     Project   : Project_1
**     Processor : MC9S08QD4CSC
**     Version   : Bean 01.026, Driver 01.27, CPU db: 2.87.049
**     Compiler  : CodeWarrior HCS08 C Compiler
**     Date/Time : 2008-3-5, 8:49
**     Abstract  :
**         This bean "MC9S08QD4_8" contains initialization of the
**         CPU and provides basic methods and events for CPU core
**         settings.
**     Settings  :
**
**
**     (c) Copyright UNIS, spol. s r.o. 1997-2006
**     UNIS, spol. s r.o.
**     Jundrovska 33
**     624 00 Brno
**     Czech Republic
**     http      : www.processorexpert.com
**     mail      : [e-mail]
** ###################################################################*/


#include "Cpu.h"
extern near void _EntryPoint(void);

void (* near const _vect[])() @0xFFD0 = { /* Interrupt vector table */
         Cpu_Interrupt,                /* Int.no.  0 Vrti (at FFD0)                  Unassigned */
         Cpu_Interrupt,                /* Int.no.  1 Reserved1 (at FFD2)             Unassigned */
         Cpu_Interrupt,                /* Int.no.  2 Reserved2 (at FFD4)             Unassigned */
         Cpu_Interrupt,                /* Int.no.  3 Reserved3 (at FFD6)             Unassigned */
         Cpu_Interrupt,                /* Int.no.  4 Vadc1 (at FFD8)                 Unassigned */
         Cpu_Interrupt,                /* Int.no.  5 Vkeyboard1 (at FFDA)            Unassigned */
         Cpu_Interrupt,                /* Int.no.  6 Reserved6 (at FFDC)             Unassigned */
         Cpu_Interrupt,                /* Int.no.  7 Reserved7 (at FFDE)             Unassigned */
         Cpu_Interrupt,                /* Int.no.  8 Reserved8 (at FFE0)             Unassigned */
         Cpu_Interrupt,                /* Int.no.  9 Reserved9 (at FFE2)             Unassigned */
         Cpu_Interrupt,                /* Int.no. 10 Reserved10 (at FFE4)            Unassigned */
         Cpu_Interrupt,                /* Int.no. 11 Reserved11 (at FFE6)            Unassigned */
         Cpu_Interrupt,                /* Int.no. 12 Reserved12 (at FFE8)            Unassigned */
         Cpu_Interrupt,                /* Int.no. 13 Vtpm2ovf (at FFEA)              Unassigned */
         Cpu_Interrupt,                /* Int.no. 14 Reserved14 (at FFEC)            Unassigned */
         Cpu_Interrupt,                /* Int.no. 15 Vtpm2ch0 (at FFEE)              Unassigned */
         Cpu_Interrupt,                /* Int.no. 16 Vtpm1ovf (at FFF0)              Unassigned */
         Cpu_Interrupt,                /* Int.no. 17 Vtpm1ch1 (at FFF2)              Unassigned */
         Cpu_Interrupt,                /* Int.no. 18 Vtpm1ch0 (at FFF4)              Unassigned */
         Cpu_Interrupt,                /* Int.no. 19 Reserved19 (at FFF6)            Unassigned */
         Cpu_Interrupt,                /* Int.no. 20 Virq (at FFF8)                  Unassigned */
         Cpu_Interrupt,                /* Int.no. 21 Vlvd (at FFFA)                  Unassigned */
         Cpu_Interrupt,                /* Int.no. 22 Vswi (at FFFC)                  Unassigned */
         _EntryPoint                   /* Int.no. 23 Vreset (at FFFE)                Reset vector */
 };
/*
** ###################################################################
**
**     This file was created by UNIS Processor Expert 3.00 [03.89]
**     for the Freescale HCS08 series of microcontrollers.
**
** ###################################################################
*/