📄 defines.c
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/*****************************************************************************
*
* Atmel Corporation
*
* File : Defines.c
* Compiler : IAR EWAAVR 3.10C
* Revision : $Revision: 1.31 $
* Date : $Date: Friday, July 02, 2004 11:13:12 UTC $
* Updated by : $Author: kmeyer $
*
* Support mail : avr@atmel.com
*
* Supported devices : This example is written for the ATmega88. Firmware
* as such should fit in any other AVR with 8kB Flash.
*
* AppNote : AVR465: Single-Phase Power/Energy Meter with
* Tamper Detection.
*
* Description : This file includes definitions used by the main file.
*
****************************************************************************/
/////////////////////////////////////////////////////////////////////////////
// D E F I N E S
/////////////////////////////////////////////////////////////////////////////
// Use internal voltage reference + external stabilising capacitors
#define ADC_VREF_TYPE 0xC0
// Masks for output signals
//
// PORT | MASK | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0 |
// -----+------+------+------+------+------+------+------+------+------+
// B | 0x03 | 0 | 0 | 0 | 0 | 0 | 0 | EP | DUTY |
// C | 0x18 | 0 | 0 | 0 |REVDIR| EARTH| 0 | 0 | 0 |
// D | 0xFC | DPN | DPP | GAIN | GAIN | GAIN | GAIN | 0 | 0 |
#define DUTY 0x01
#define EP 0x02
#define EARTH 0x08
#define REVDIR 0x10
#define DPP 0x40
#define DPN 0x80
#define DIRB 0x03
#define DIRC 0x18
#define DIRD 0xFC
// Gain stage control constants
#define ADC0 0
#define ADC1 1
#define LOW 0
#define MEDIUM 1
#define HIGH 2
// Step up gain when amplitude of FILTERED signal drops below AMP_LO.
// Assuming 8.000x gain, the threshold may not be set higher than:
//
// AMP_LO(max) = 255 * [(1023/2) / 8] = 16304d = 3FB0h
//
// Measurement results indicate 1% accuracy can be reached at amplitudes as
// low as 25, at unity power factor. Leaving some headroom for 0.5 power
// factor measurements, the recommended minimum is:
//
// AMP_LO(min) = 255*50 = approx 3200h
#define AMP_LO 0x3200
// Step down gain when UNCONDITIONED data is below SAT_LO or above SAT_HI
#define SAT_LO 0x0007
#define SAT_HI 0x03F8
// Wait GAIN_HOLD samples after range switch before allowing new switch
#define GAIN_HOLD 480
// Starting current in amps: this should be no more than 0.002 x base current
#define I_MIN 0.002
// Power threshold in watts: disable tamper logic when active power below this
#define P_MIN 1.000
// Constant offset, which is added to sampled data. Should not be more than
// 1/2 LSB*255, typically OFFSET = 80h. Else transfer funtion may grow non-
// linear (especially at power factors other than 1).
#define OFFSET 0x80
// Flags
#define DISPLAY 0x01
#define GROGGY 0x02
#define KEY_PRESSED 0x04
#define CYCLE_FULL 0x08
#define MOREGAIN0 0x10
#define LESSGAIN0 0x20
#define MOREGAIN1 0x40
#define LESSGAIN1 0x80
// Number of samples that will be accumulated for measurements. Since measure-
// ments are based on a fixed time window, the accumulation cycle should be
// such that it fits an integer number of mains cycles. Otherwise, measurement
// results will fluctuate and create short-term variations. Even so, the
// effects can be completely removed by means of averaging the measurement
// results. No harm done in the long run, but may look strange and gives a
// false impression of poor accuracy.
//
// For compliancy with both 50Hz and 60Hz environments, the cycle length
// should be chosen such, that it can fit an integer number of both 50Hz and
// 60Hz signals. For example, cycle lengths of 200ms multiples are fine.
// Some suitable cycle lengths are as follows:
//
// XTAL | ADC | ADCCLK | Sampling | S.R./Ch | Cycle | 50Hz | 60Hz
// [MHz] | Presc | [Hz] | Rate [Hz] | [Hz] | Length | Cycles | Cycles
// ------+-------+--------+-----------+---------+--------+---------+--------
// 3.580 | 128 | 27965 | 2151.169 | 717.06 | N*72 | N*5.021 | N*6.025
// 3.689 | 128 | 28800 | 2215.385 | 738.46 | N*74 | N*5.010 | N*6.012
// 4.000 | 128 | 31250 | 2403.846 | 801.28 | N*80 | N*4.999 | N*5.999
// -"- | -"- | -"- | -"- | -"- | 80 | 4.9920 | 5.9904
// -"- | -"- | -"- | -"- | -"- | 401 | 25.0225 | 30.0270
// 4.096 | 128 | 32000 | 2461.538 | 820.51 | N*82 | N*5.000 | N*6.000
// 4.608 | 128 | 36000 | 2769.231 | 923.08 | N*92 | N*4.983 | N*5.980
#define NMAX 401
#define NORM 1.0/NMAX
// This is the length of pulses DPP and DPN, measured in sampling periods.
// For example, DP_ON=241 at sampling rate 2403Hz results in pulse lengths
// of (241-1)/2403 = 0.100s.
#define DP_ON 241
// Polynome used in CRC calculations
#define CRC_POLYNOME 0x8005
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