spi850.c

vxworks下MPC860的SPI操作源码

/* spi850.c - MPC850 CPM's SPI driver ported from 'wpbx' project
 *
 * Descript: This driver read and write regiter by polling.
 * Copyright 2005 StelCom, Inc. 
 * creater: xujian 2005/8/18
 */


#include "mospub.h"

#include "spi850.h"
#include "peb3265/peb3265_def.h"

volatile U8*  txbuf;
volatile U8*  rxbuf;
volatile U8  *txptr,*rxptr;
volatile U32 ulSpiFails=0;
 
extern U32 vxImmrGet(void);
void spi850_setup_tx_rx_bds(U16 len);
U32 spi850_wait_for_tx_rx(U32 immrVal);
void spi850_move_ucode(void);


/***********************************************************************/
/* spi8xx_init(): Initialize the SPI device on the MPC8xx CPU          */
/*                                                                     */
/*      INPUTS: None                                                   */
/*                                                                     */
/*     RETURNS:                                                        */
/*     OUTPUTS:                                                        */
/*     NOTE(S):                                                        */
/*                                                                     */
/***********************************************************************/
void spi850_init()
{
    U16 ulTmp;
    volatile U32    dpr_spi_base, immrVal;
    
/*---------------------------------------------------------------------*/
/* Begin initialization with the SPI disabled.                         */
/*---------------------------------------------------------------------*/
    immrVal = vxImmrGet();/*get current IMMR value :IMMR:internal memory map register*/
  
    *SPMODE(immrVal) = 0;/*disable this spi,*/
    /**SDMR(immrVal) = 1;//SDMA Mask Register,*/

    *RCCR(immrVal) = 0;		/* Disable microcode program area */
    #if USE_SET
    spi850_move_ucode();    /* Copy microcode patch to DPRAM. */

    *RCTR1(immrVal) = 0x802a;	/* Write Trap register 1 value.           */
    *RCTR2(immrVal) = 0x8028;	/* Write Trap register 2 value.           */

    *RCCR(immrVal) = 0x1;		/* Enable DPRAM microcode to execute from */
        						/* the first 512 bytes and a 256 byte     */
    #endif

/*---------------------------------------------------------------------*/
/* Setup SPI parameter RAM.                                            */
/*---------------------------------------------------------------------*/
	/*write RBASE and TBASE in the SPI parameter RAM to point to the */
	/*RxBD and TxBD tables in the Dual-port RAM*/
	/*PPC860_DPR_SPI:相对于MPC860的偏移由SPI_BASE寄存器设置*/
	#if USE_SET
    *SPI_BASE(immrVal) = SPI_PARAMETER_RAM_OFF;
    #endif
    dpr_spi_base = (volatile U32)PPC860_DPR_SPI(immrVal);
    *SPI_RBASE(dpr_spi_base) = SPI_RX_BD;
    *SPI_TBASE(dpr_spi_base) = SPI_TX_BD;

/*---------------------------------------------------------------------*/
/* Make the buffers word aligned                                       */
/*---------------------------------------------------------------------*/
    txbuf = (U8*)(immrVal+SPI_TX_BUFF);
    rxbuf = (U8*)(immrVal+SPI_RX_BUFF);
    txptr =(U8*) txbuf;
    rxptr =(U8*) rxbuf;
    spi850_setup_tx_rx_bds(0);

    /*Write RFCR and TFCR with 0x10 for normal operation.*/
    *SPI_RFCR(dpr_spi_base) = RFCR_BO_BE;/*RFCR_BO_MOT_BE; 0x10:big endian mode*/
    *SPI_TFCR(dpr_spi_base) = RFCR_BO_BE;/*RFCR_BO_MOT_BE; 0x10:big endian mode */
    *SPI_MRBLR(dpr_spi_base) = SPI_Rx_Tx_BUFF_LEN;/*maxinum number of bytes per Rx buff*/

    *SPI_RSTATE(dpr_spi_base) = 0;
    *SPI_RBPTR(dpr_spi_base) = SPI_RX_BD;
    *SPI_TSTATE(dpr_spi_base) = 0;
    *SPI_TBPTR(dpr_spi_base) = SPI_TX_BD;

/*---------------------------------------------------------------------*/
/* Clear any pre-existing events and mask all future SPI events.       */
/*---------------------------------------------------------------------*/
    *SPIE(immrVal) = 0xFF;
    *SPIM(immrVal)  = 0;
/*---------------------------------------------------------------------*/
/* Enable the SPI as master with 8-bit words and a clock rate of slow  */
/*---------------------------------------------------------------------*/
    *SPMODE(immrVal) =  SPMODE_MS + SPMODE_EN
             + SPMODE_CP+SPMODE_CI+SPMODE_REV 
             + ((8 - 1) << 4) + 4;    
}

/***********************************************************************/
/* spi850_setup_tx_rx_bds: Setup the buffer descriptors required for the SPI  */
/*                                                                     */
/*      INPUTS: len                                                    */
/*                                                                     */
/*     RETURNS:                                                        */
/*     OUTPUTS:                                                        */
/*     NOTE(S):                                                        */
/*                                                                     */
/***********************************************************************/
void spi850_setup_tx_rx_bds(U16 len)
{
    volatile U32 immrVal;
    SPI_BUF* pSpiTxBd;
    SPI_BUF* pSpiRxBd;

    immrVal = vxImmrGet();

    pSpiTxBd = (SPI_BUF*)(immrVal + SPI_TX_BD);
    pSpiRxBd = (SPI_BUF*)(immrVal + SPI_RX_BD);
    
    pSpiTxBd->statusMode = SPI_TX_BD_R + SPI_TX_BD_W + SPI_TX_BD_L +SPI_TX_BD_I;
    pSpiTxBd->dataLength = len;
    pSpiTxBd->dataPointer = txptr;

    pSpiRxBd->statusMode = SPI_RX_BD_E + SPI_RX_BD_W + SPI_RX_BD_I;
    pSpiRxBd->dataLength = 0;
    pSpiRxBd->dataPointer = rxptr;

}

/***********************************************************************/
/* spi850_wait_for_tx_rx: Wait the tx and then for rx event to occur.  */
/*                                                                     */
/*      INPUTS: None                                                   */
/*                                                                     */
/*     RETURNS:0:if Succ,FAIL:if Fail                                  */
/*     OUTPUTS:                                                        */
/*     NOTE(S):                                                        */
/*                                                                     */
/***********************************************************************/
U32 spi850_wait_for_tx_rx(U32 immrVal)
{
    U32 i;
  
    for( i = 0; i< 5000; i++ )
    {
        if((i%10) == 0)
        {
            if( (*SPIE(immrVal)) & SPI_SPIE_RXB )
            {
                break;
            }
        }
    }
    if (5000 == i)
    {
        ulSpiFails++;
        spi850_init();
        mos_log_msg("Recv Timeout .Init 850 spi. SPIE = 0x%x.\r\n",*SPIE(immrVal));
        return FAIL;
    }

    return SUCC;
}


void spi850_move_ucode(void)
{
    volatile U32 immr;
    U32 i;

    immr = vxImmrGet();
    
*((U32 *)(immr + 0x2000)) = 0x7fffefd9;
*((U32 *)(immr + 0x2004)) = 0x3ffd0000;
*((U32 *)(immr + 0x2008)) = 0x7ffb49f7;
*((U32 *)(immr + 0x200c)) = 0x7ff90000;
*((U32 *)(immr + 0x2010)) = 0x5fefadf7;
*((U32 *)(immr + 0x2014)) = 0x5f88adf7;
*((U32 *)(immr + 0x2018)) = 0x5fefaff7;
*((U32 *)(immr + 0x201c)) = 0x5f88aff7;
*((U32 *)(immr + 0x2020)) = 0x3a9cfbc8;
*((U32 *)(immr + 0x2024)) = 0x77cae1bb;
*((U32 *)(immr + 0x2028)) = 0xf4de7fad;
*((U32 *)(immr + 0x202c)) = 0xabae9330;
*((U32 *)(immr + 0x2030)) = 0x4e08fdcf;
*((U32 *)(immr + 0x2034)) = 0x6e0faff8;
*((U32 *)(immr + 0x2038)) = 0x7ccf76cf;
*((U32 *)(immr + 0x203c)) = 0xfdaff9cf;
*((U32 *)(immr + 0x2040)) = 0xabf88dc8;
*((U32 *)(immr + 0x2044)) = 0xab5879f7;
*((U32 *)(immr + 0x2048)) = 0xb0926a27;
*((U32 *)(immr + 0x204c)) = 0xdfd079f7;
*((U32 *)(immr + 0x2050)) = 0xb090e6bb;
*((U32 *)(immr + 0x2054)) = 0xe5bbe74f;
*((U32 *)(immr + 0x2058)) = 0xaa616f0f;
*((U32 *)(immr + 0x205c)) = 0x6ffb76ce;
*((U32 *)(immr + 0x2060)) = 0xee0cf9cf;
*((U32 *)(immr + 0x2064)) = 0x2bfbefef;
*((U32 *)(immr + 0x2068)) = 0xcfeef9cf;
*((U32 *)(immr + 0x206c)) = 0x76cead23;
*((U32 *)(immr + 0x2070)) = 0x90b3df99;
*((U32 *)(immr + 0x2074)) = 0x7fddd0c1;
*((U32 *)(immr + 0x2078)) = 0x4bf847fd;
*((U32 *)(immr + 0x207c)) = 0x7ccf76ce;
*((U32 *)(immr + 0x2080)) = 0xcfef77ca;
*((U32 *)(immr + 0x2084)) = 0x7eaf7fad;
*((U32 *)(immr + 0x2088)) = 0x7dfdf0b7;
*((U32 *)(immr + 0x208c)) = 0xef7a7fca;
*((U32 *)(immr + 0x2090)) = 0x77cafbc8;
*((U32 *)(immr + 0x2094)) = 0x6079e722;
*((U32 *)(immr + 0x2098)) = 0xfbc85fff;
*((U32 *)(immr + 0x209c)) = 0xdfff5fb3;
*((U32 *)(immr + 0x20a0)) = 0xfffbfbc8;
*((U32 *)(immr + 0x20a4)) = 0xf3c894a5;
*((U32 *)(immr + 0x20a8)) = 0xe7c9edf9;
*((U32 *)(immr + 0x20ac)) = 0x7f9a7fad;
*((U32 *)(immr + 0x20b0)) = 0x5f36afe8;
*((U32 *)(immr + 0x20b4)) = 0x5f5bffdf;
*((U32 *)(immr + 0x20b8)) = 0xdf95cb9e;
*((U32 *)(immr + 0x20bc)) = 0xaf7d5fc3;
*((U32 *)(immr + 0x20c0)) = 0xafed8c1b;
*((U32 *)(immr + 0x20c4)) = 0x5fc3afdd;
*((U32 *)(immr + 0x20c8)) = 0x5fc5df99;
*((U32 *)(immr + 0x20cc)) = 0x7efdb0b3;
*((U32 *)(immr + 0x20d0)) = 0x5fb3fffe;
*((U32 *)(immr + 0x20d4)) = 0xabae5fb3;
*((U32 *)(immr + 0x20d8)) = 0xfffe5fd0;
*((U32 *)(immr + 0x20dc)) = 0x600be6bb;
*((U32 *)(immr + 0x20e0)) = 0x600b5fd0;
*((U32 *)(immr + 0x20e4)) = 0xdfc827fb;
*((U32 *)(immr + 0x20e8)) = 0xefdf5fca;
*((U32 *)(immr + 0x20ec)) = 0xcfde3a9c;
*((U32 *)(immr + 0x20f0)) = 0xe7c9edf9;
*((U32 *)(immr + 0x20f4)) = 0xf3c87f9e;
*((U32 *)(immr + 0x20f8)) = 0x54ca7fed;
*((U32 *)(immr + 0x20fc)) = 0x2d3a3637;
*((U32 *)(immr + 0x2100)) = 0x756f7e9a;
*((U32 *)(immr + 0x2104)) = 0xf1ce37ef;
*((U32 *)(immr + 0x2108)) = 0x2e677fee;
*((U32 *)(immr + 0x210c)) = 0x10ebadf8;
*((U32 *)(immr + 0x2110)) = 0xefdecfea;
*((U32 *)(immr + 0x2114)) = 0xe52f7d9f;
*((U32 *)(immr + 0x2118)) = 0xe12bf1ce;
*((U32 *)(immr + 0x211c)) = 0x5f647e9a;
*((U32 *)(immr + 0x2120)) = 0x4df8cfea;
*((U32 *)(immr + 0x2124)) = 0x5f717d9b;
*((U32 *)(immr + 0x2128)) = 0xefeecfea;
*((U32 *)(immr + 0x212c)) = 0x5f73e522;
*((U32 *)(immr + 0x2130)) = 0xefde5f73;
*((U32 *)(immr + 0x2134)) = 0xcfda0b61;
*((U32 *)(immr + 0x2138)) = 0x6a29df61;
*((U32 *)(immr + 0x213c)) = 0xe7c9edf9;
*((U32 *)(immr + 0x2140)) = 0x7e9a30d5;
*((U32 *)(immr + 0x2144)) = 0x1458bfff;
*((U32 *)(immr + 0x2148)) = 0xf3c85fff;
*((U32 *)(immr + 0x214c)) = 0xdfffa7f8;
*((U32 *)(immr + 0x2150)) = 0x5f5bbffe;
*((U32 *)(immr + 0x2154)) = 0x7f7d10d0;
*((U32 *)(immr + 0x2158)) = 0x144d5f33;
*((U32 *)(immr + 0x215c)) = 0xbfffaf78;
*((U32 *)(immr + 0x2160)) = 0x5f5bbffd;
*((U32 *)(immr + 0x2164)) = 0xa7f85f33;
*((U32 *)(immr + 0x2168)) = 0xbffe77fd;
*((U32 *)(immr + 0x216c)) = 0x30bd4e08;
*((U32 *)(immr + 0x2170)) = 0xfdcfe5ff;
*((U32 *)(immr + 0x2174)) = 0x6e0faff8;
*((U32 *)(immr + 0x2178)) = 0x7eef7e9f;
*((U32 *)(immr + 0x217c)) = 0xfdeff1cf;
*((U32 *)(immr + 0x2180)) = 0x5f17abf8;
*((U32 *)(immr + 0x2184)) = 0x0d5b5f5b;
*((U32 *)(immr + 0x2188)) = 0xffef79f7;
*((U32 *)(immr + 0x218c)) = 0x309eafdd;
*((U32 *)(immr + 0x2190)) = 0x5f3147f8;
*((U32 *)(immr + 0x2194)) = 0x5f31afed;
*((U32 *)(immr + 0x2198)) = 0x7fdd50af;
*((U32 *)(immr + 0x219c)) = 0x497847fd;
*((U32 *)(immr + 0x21a0)) = 0x7f9e7fed;
*((U32 *)(immr + 0x21a4)) = 0x7dfd70a9;
*((U32 *)(immr + 0x21a8)) = 0xef7e7ece;
*((U32 *)(immr + 0x21ac)) = 0x6ba07f9e;
*((U32 *)(immr + 0x21b0)) = 0x2d227efd;
*((U32 *)(immr + 0x21b4)) = 0x30db5f5b;
*((U32 *)(immr + 0x21b8)) = 0xfffd5f5b;
*((U32 *)(immr + 0x21bc)) = 0xffef5f5b;
*((U32 *)(immr + 0x21c0)) = 0xffdf0c9c;
*((U32 *)(immr + 0x21c4)) = 0xafed0a9a;
*((U32 *)(immr + 0x21c8)) = 0xafdd0c37;
*((U32 *)(immr + 0x21cc)) = 0x5f37afbd;
*((U32 *)(immr + 0x21d0)) = 0x7fbdb081;
*((U32 *)(immr + 0x21d4)) = 0x5f8147f8;
*((U32 *)(immr + 0x2f00)) = 0x3e303430;
*((U32 *)(immr + 0x2f04)) = 0x34343737;
*((U32 *)(immr + 0x2f08)) = 0xabbf9b99;
*((U32 *)(immr + 0x2f0c)) = 0x4b4fbdbd;
*((U32 *)(immr + 0x2f10)) = 0x59949334;
*((U32 *)(immr + 0x2f14)) = 0x9fff37fb;
*((U32 *)(immr + 0x2f18)) = 0x9b177dd9;
*((U32 *)(immr + 0x2f1c)) = 0x936956bb;
*((U32 *)(immr + 0x2f20)) = 0xfbdd697b;
*((U32 *)(immr + 0x2f24)) = 0xdd2fd113;
*((U32 *)(immr + 0x2f28)) = 0x1db9f7bb;
*((U32 *)(immr + 0x2f2c)) = 0x36313963;
*((U32 *)(immr + 0x2f30)) = 0x79373369;
*((U32 *)(immr + 0x2f34)) = 0x3193137f;
*((U32 *)(immr + 0x2f38)) = 0x7331737a;
*((U32 *)(immr + 0x2f3c)) = 0xf7bb9b99;
*((U32 *)(immr + 0x2f40)) = 0x9bb19795;
*((U32 *)(immr + 0x2f44)) = 0x77fdfd3d;
*((U32 *)(immr + 0x2f48)) = 0x573b773f;
*((U32 *)(immr + 0x2f4c)) = 0x737933f7;
*((U32 *)(immr + 0x2f50)) = 0xb991d115;
*((U32 *)(immr + 0x2f54)) = 0x31699315;
*((U32 *)(immr + 0x2f58)) = 0x31531694;
*((U32 *)(immr + 0x2f5c)) = 0xbf4fbdbd;
*((U32 *)(immr + 0x2f60)) = 0x35931497;
*((U32 *)(immr + 0x2f64)) = 0x35376956;
*((U32 *)(immr + 0x2f68)) = 0xbd697b9d;
*((U32 *)(immr + 0x2f6c)) = 0x96931313;
*((U32 *)(immr + 0x2f70)) = 0x19797937;
*((U32 *)(immr + 0x2f74)) = 0x69350000;

  return;
}


void  peb3265_reset_init(void)
{
    volatile U32 immrVal;    

    immrVal = vxImmrGet();

    /* SPI peripheral fuction port */
    *PBPAR(immrVal) |=  (PB28 | PB29 | PB30);/*use as a general-purpose I/O port*/
    *PBDIR(immrVal) |=  (PB28 | PB29 | PB30);/*select peripheral fuction 1*/
    *PBODR(immrVal) &= ~(PB28 | PB29 | PB30);/**/

    /* CS_SPI */    
    *PBPAR(immrVal) &= ~(PB31);/*设置为0,表示通用目的*/
    *PBDIR(immrVal) |= PB31;/*设置为1,表示Out*/
    *PBDAT(immrVal) |= PB31;
    #if APP_MPC852
    /* RESET_DEVICE            */
    *PAPAR(immrVal) &= ~PA10;/*设置为0,表示通用目的*/
    *PADIR(immrVal) |= PA10;/*设置为1,表示Out*/
    *PADAT(immrVal) |= PA10;

    /* SEL2->PC6