📄 at91sam7xc128_bga100.bsd
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-------------------------------------------------------------------------- A T M E L A R M M I C R O C O N T R O L L E R S ---------------------------------------------------------------------------- BSDL file---- File Name: AT91SAM7XC128_BGA100.BSD-- File Revision: 1.0-- Date: 01 Oct 2007-- Created by: Atmel Corporation-- File Status: Released---- Device: AT91SAM7XC128-- Package: TFBGA100---- Visit http://www.atmel.com for a updated list of BSDL files.---------------------------------------------------------------------------- Syntax and Semantics are checked against the IEEE 1149.1 standard. ---- The logical functioning of the standard Boundary-Scan instructions ---- and of the associated bypass, idcode and boundary-scan register ---- described in this BSDL file has been verified against its related ---- silicon by JTAG Technologies B.V. ---------------------------------------------------------------------------------------------------------------------------------------------------- IMPORTANT NOTICE ---- ---- Copyright 2007 Atmel Corporation. All Rights Reserved. ---- ---- Atmel assumes no responsibility or liability arising out ---- this application or use of any information described herein ---- except as expressly agreed to in writing by Atmel Corporation. ---- ---- ------------------------------------------------------------------ ---- This BSDL File has been verified on Agilent Asset BSDL Syntax ---- Checker/Compiler: ---- Job Status: Pass ---- ---- File Name: AT91SAM7XC128_BGA100.bsd ---- Timestamp: Monday, October 01, 2007 9:07 AM ---- ---- Results: Entity name: AT91SAM7XC128 ---- IEEE Std 1149.1-1994 (Version 1.0) ---- Packaging option selected is TFBGA100_O_270X277. ---- Inputs = 1 ---- Outputs = 0 ---- Bidirectionals = 62 ---- Instruction Reg Length = 3 ---- Boundary Reg Length = 187 ---- ---- BSDL compilation of 494 lines completed without errors. ---- ---- There were 1 compile warnings. ---- Text of warnings: ---- Warning: No Linkage signals (e.g. power pins) found in port or pin_map---- -------------------------------------------------------------------------- entity AT91SAM7XC128 is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "TFBGA100_O_270x277"); -- This section declares all the ports in the design. port ( erase : in bit; icetck : in bit; icetdi : in bit; icetms : in bit; jtagsel : in bit; nrst : in bit; test : in bit; pa0 : inout bit; pa1 : inout bit; pa10 : inout bit; pa11 : inout bit; pa12 : inout bit; pa13 : inout bit; pa14 : inout bit; pa15 : inout bit; pa16 : inout bit; pa17 : inout bit; pa18 : inout bit; pa19 : inout bit; pa2 : inout bit; pa20 : inout bit; pa21 : inout bit; pa22 : inout bit; pa23 : inout bit; pa24 : inout bit; pa25 : inout bit; pa26 : inout bit; pa27 : inout bit; pa28 : inout bit; pa29 : inout bit; pa3 : inout bit; pa30 : inout bit; pa4 : inout bit; pa5 : inout bit; pa6 : inout bit; pa7 : inout bit; pa8 : inout bit; pa9 : inout bit; pb0 : inout bit; pb1 : inout bit; pb10 : inout bit; pb11 : inout bit; pb12 : inout bit; pb13 : inout bit; pb14 : inout bit; pb15 : inout bit; pb16 : inout bit; pb17 : inout bit; pb18 : inout bit; pb19 : inout bit; pb2 : inout bit; pb20 : inout bit; pb21 : inout bit; pb22 : inout bit; pb23 : inout bit; pb24 : inout bit; pb25 : inout bit; pb26 : inout bit; pb27 : inout bit; pb28 : inout bit; pb29 : inout bit; pb3 : inout bit; pb30 : inout bit; pb4 : inout bit; pb5 : inout bit; pb6 : inout bit; pb7 : inout bit; pb8 : inout bit; pb9 : inout bit; icetdo : out bit ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of AT91SAM7XC128: entity is "STD_1149_1_1993"; attribute PIN_MAP of AT91SAM7XC128: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information-- is extracted from the port-to-pin map file that was read in using-- the "read_pin_map" command. constant TFBGA100_O_270x277: PIN_MAP_STRING := "erase : F7," & "icetck : F5," & "icetdi : B1," & "icetms : E5," & "jtagsel : H3," & "nrst : D3," & "test : D4," & "pa0 : J3," & "pa1 : J4," & "pa10 : D7," & "pa11 : D10," & "pa12 : C9," & "pa13 : C8," & "pa14 : B8," & "pa15 : C10," & "pa16 : B9," & "pa17 : B10," & "pa18 : A9," & "pa19 : B2," & "pa2 : G5," & "pa20 : A3," & "pa21 : A2," & "pa22 : A1," & "pa23 : D1," & "pa24 : D2," & "pa25 : E1," & "pa26 : E2," & "pa27 : G3," & "pa28 : H2," & "pa29 : J1," & "pa3 : H4," & "pa30 : J2," & "pa4 : H5," & "pa5 : G6," & "pa6 : F6," & "pa7 : H6," & "pa8 : H8," & "pa9 : H7," & "pb0 : C5," & "pb1 : A4," & "pb10 : C3," & "pb11 : B3," & "pb12 : B5," & "pb13 : C7," & "pb14 : B7," & "pb15 : B6," & "pb16 : C1," & "pb17 : C6," & "pb18 : E3," & "pb19 : D5," & "pb2 : B4," & "pb20 : E4," & "pb21 : F1," & "pb22 : G1," & "pb23 : F2," & "pb24 : G2," & "pb25 : F3," & "pb26 : F4," & "pb27 : D9," & "pb28 : E8," & "pb29 : H9," & "pb3 : C4," & "pb30 : G9," & "pb4 : C2," & "pb5 : A6," & "pb6 : D6," & "pb7 : A5," & "pb8 : A7," & "pb9 : A8," & "icetdo : G4"; -- This section specifies the TAP ports.-- For the TAP TCK port, the parameters in the brackets are:-- First Field : Maximum TCK frequency.-- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of icetck: signal is (10.0e6, BOTH); attribute TAP_SCAN_IN of icetdi: signal is true; attribute TAP_SCAN_MODE of icetms: signal is true; attribute TAP_SCAN_OUT of icetdo: signal is true; attribute TAP_SCAN_RESET of nrst : signal is true; -- Specifies the compliance enable patterns for the design.-- It lists a set of design ports and the values that they-- should be set to, in order to enable compliance to IEEE-- Std 1149.1 attribute COMPLIANCE_PATTERNS of AT91SAM7XC128: entity is "(jtagsel, test) (10)"; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of AT91SAM7XC128: entity is 3; -- Specifies the boundary-scan instructions implemented in the-- design and their opcodes. attribute INSTRUCTION_OPCODE of AT91SAM7XC128: entity is "BYPASS (111)," &⌨️ 快捷键说明
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