sync_dl_phasemodule.vhd

td-scdma仿真

-----------------------------------------------------------------------------
-- sync_dl_phasemodule.vhd
----------------------------------------------------------------------------- 
--
-- Copyright (c) 2005 WSPN@BUPT.
-- Proprietary and Confidential Information.
-- Not to be copied or distributed.
--
----------------------------------------------------------------------------- 
--
-- Description: 
-- 		Phase modulation for DwPTS.
--		According to 3GPP TS 25.223.
--
----------------------------------------------------------------------------- 

entity sync_dl_phasemodule is
     generic(ctrlPortSlotRate      : integer := 128;
             OutPortSlotRate       : integer := 64);
  port (sync_dl_phasemodule_inPortsl:in integer32@ctrlPortSlotRate;
        sync_dl_phasemodule_outPort:out complex16@OutPortSlotRate);
end entity sync_dl_phasemodule;

architecture C of sync_dl_phasemodule is
begin STAN2 "-O2"
  CODE
int main()
{
  int i,j,k;    
  int angle_table_one[8] = {-1,1,1,1,-1,-1,-1,1};//real&imag alternate
  int angle_table_two[8] = {1,-1,-1,-1,1,-1,1,1};
  int sync_DL_modulated_i,sync_DL_modulated_q;

  complex16 syncOut;
  int *tempP;
  int phaseShift;

  int sync_DL,sync_DL_phase;
  int phase_flag;
//1-->0,+j-->1,-1-->2,-j-->3
  integer32 sigling;
  unsigned int sync_DL_table[4]={0XB3A7,0XCC05,0XA986,0X88E4};
  while(1)
  {
    sigling = getsync_dl_phasemodule_inPortsl();
    phase_flag = sigling&1;

    if(phase_flag==0) //There is a P-CCPCH in the next 4 sub-frames
    {
        tempP = angle_table_one;
    }
    else
    {
        tempP = angle_table_two;
    }


	for(k=0;k<4;k++)	// 4 radioframe(20ms)
    {
		phaseShift = k+k;
		for(i=0;i<4;i++)	// array sync_DL_table has 4 element
		{
        	for(j=0;j<16;j++)	// each element of sync_DL_table has 16 bits
        	{
				sync_DL = 2*((sync_DL_table[i]>>(15-j))&1)-1;     //0-->-1,1-->+1
				sync_DL = sync_DL * 2350;
				//putsync_dl_phasemodule_outPort(sync_DL);
				sync_DL_phase = (i*16+j+1)&3;	

				/* Mapping is used here,
				   j => PI/2 => 1,
				   -1 => PI => 2
				   -j => 3*PI/2 => 3,
				   1 => 0 => 0 */
				if(sync_DL_phase == 1)
				{
					syncOut.re = -(*(tempP+phaseShift+1))*sync_DL;
					syncOut.im = (*(tempP+phaseShift))*sync_DL;
					putsync_dl_phasemodule_outPort(syncOut);
				}
				else if(sync_DL_phase == 2)
				{
					syncOut.re = -(*(tempP+phaseShift))*sync_DL;
					syncOut.im = -(*(tempP+phaseShift+1))*sync_DL;
					putsync_dl_phasemodule_outPort(syncOut);
				}
				else if(sync_DL_phase == 3)
				{
					syncOut.re = (*(tempP+phaseShift+1))*sync_DL;
					syncOut.im = -(*(tempP+phaseShift))*sync_DL;
					putsync_dl_phasemodule_outPort(syncOut);
				}
				else
				{
					syncOut.re = (*(tempP+phaseShift))*sync_DL;
					syncOut.im = (*(tempP+phaseShift+1))*sync_DL;
					putsync_dl_phasemodule_outPort(syncOut);
				}

        }//end of j
      }//end of i
    }//end of k
  }//end of while
  return 0;
}//end of main
  ENDCODE;
end sync_dl_phasemodule;

--entity sync_dl_phasemodule is
--     generic(ctrlPortSlotRate      : integer := 128;
--             OutPortSlotRate       : integer := 64);
--  port (sync_dl_phasemodule_inPortsl:in integer32@ctrlPortSlotRate;
--        sync_dl_phasemodule_outPort:out complex16@OutPortSlotRate);//send to "sync_dl_send" module
--end entity sync_dl_phasemodule;

--architecture C of sync_dl_phasemodule is
--begin STAN2 "-O2"
--  CODE
--int main()
--{
--  int i,j,k;    
--  int angle_table_one[8] = {-1,1,1,1,-1,-1,-1,1};//real&imag alternate
--  int angle_table_two[8] = {1,-1,-1,-1,1,-1,1,1};
--  int sync_DL_modulated_i,sync_DL_modulated_q;

--  complex16 syncOut;

--  int sync_DL,sync_DL_phase;
--  int phase_flag;
--//1-->0,+j-->1,-1-->2,-j-->3
--  integer32 sigling;
--  unsigned int sync_DL_table[4]={0XB3A7,0XCC05,0XA986,0X88E4};
--  while(1)
--  {
--    sigling = getsync_dl_phasemodule_inPortsl();
--    phase_flag = sigling;
--    for(k=0;k<4;k++)
--    {
--      for(i=0;i<4;i++) 
--      {
--        for(j=0;j<16;j++)
--        {
--          sync_DL = 2*((sync_DL_table[i]>>(15-j))&1)-1;     //0-->-1,1-->+1
--//          putsync_dl_phasemodule_outPort(sync_DL);
--          sync_DL_phase = (i*16+j+1)&3;	
--          if(phase_flag==0) //There is a P-CCPCH in the next 4 sub-frames
--	  {
--            if(sync_DL_phase == 1)
--	    {
--              syncOut.re = -angle_table_one[2*k+1]*sync_DL;
--	      syncOut.im = angle_table_one[2*k]*sync_DL;
--	      putsync_dl_phasemodule_outPort(syncOut);
--	    }
--            else if(sync_DL_phase == 2)
--	    {
--              syncOut.re = -angle_table_one[2*k]*sync_DL;
--	      syncOut.im = -angle_table_one[2*k+1]*sync_DL;
--	      putsync_dl_phasemodule_outPort(syncOut);
--	    }
--            else if(sync_DL_phase == 3)
--	    {
--              syncOut.re = angle_table_one[2*k+1]*sync_DL;
--	      syncOut.im = -angle_table_one[2*k]*sync_DL;
--	      putsync_dl_phasemodule_outPort(syncOut);
--	    }
--            else
--	    {
--              syncOut.re = angle_table_one[2*k]*sync_DL;
--	      syncOut.im = angle_table_one[2*k+1]*sync_DL;
--	      putsync_dl_phasemodule_outPort(syncOut);
--	    }
--          }
--	  else //There is no P-CCPCH in the next 4 sub-frames
--	  {
--            if(sync_DL_phase == 1)
--	    {
--              syncOut.re = -angle_table_two[2*k+1]*sync_DL;
--	      syncOut.im = angle_table_two[2*k]*sync_DL;
--	      putsync_dl_phasemodule_outPort(syncOut);
--	    }
--            else if(sync_DL_phase == 2)
--	    {
--              syncOut.re = -angle_table_two[2*k]*sync_DL;
--	      syncOut.im = -angle_table_two[2*k+1]*sync_DL;
--	      putsync_dl_phasemodule_outPort(syncOut);
--	    }
--            else if(sync_DL_phase == 3)
--	    {
--              syncOut.re = angle_table_two[2*k+1]*sync_DL;
--	      syncOut.im = -angle_table_two[2*k]*sync_DL;
--	      putsync_dl_phasemodule_outPort(syncOut);
--	    }
--            else
--	    {
--              syncOut.re = angle_table_two[2*k]*sync_DL;
--	      syncOut.im = angle_table_two[2*k+1]*sync_DL;
--	      putsync_dl_phasemodule_outPort(syncOut);
--	    }	//end of if 
--	  }//end of else
--        }//end of j
--      }//end of i
--    }//end of k
--  }//end of while
--  return 0;
--}//end of main
--  ENDCODE;
--end sync_dl_phasemodule;




--library peripherals;
--use peripherals.all;

--use work.all;

--entity sync_dl_phasemoduleob is
--end sync_dl_phasemoduleob;

--architecture STRUCTURAL of sync_dl_phasemoduleob is
--   signal inputsl                                    :  integer32@8; 
--   signal output                                     :  integer32@8;

--begin

--  sync_dl_phasemoduledemo : entity sync_dl_phasemodule
--  port map(
--          sync_dl_phasemodule_inPortsl                 => inputsl,
--	  sync_dl_phasemodule_outPort                  => output);    
--  src0 : entity dataSrc
--    generic map (
--      sig_t      => integer32,
--      fileName   => "inputsl.txt",
--      eofDelay   => 100,
--      slotRate   => 128,
--      debugLevel => 0,
--      inputBase => "dec" )
--    port map (fileData => inputsl);

--  dst0 : entity dataSink
--    generic map (
--      sig_t      => integer32,
--      fileName   => "output.txt",
--      slotRate   => 64,
--      debugLevel => 0,
--      outputBase => "dec" )
--    port map (fileData => output);
  
--end sync_dl_phasemoduleob;