moving.vhd

FPGA控制LCD屏幕显示图像

LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY moving IS PORT
( clk    : IN std_logic;
  clken_fcount: IN std_logic;
  de_out :IN std_logic;
  pattern: IN std_logic_vector(4  DOWNTO 0);
  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_o   : OUT std_logic_vector(7 DOWNTO 0)
);
CONSTANT HAC:integer:=512;   -- horizontal active pixels
END moving;

ARCHITECTURE rtl OF moving IS
	SIGNAL m1countreg:std_logic_vector(10 DOWNTO 0);
	SIGNAL m2countreg:std_logic_vector(10 DOWNTO 0);
	SIGNAL pm_temp: std_logic;
	sIGNAL speed : STD_LOGIC_VECTOR(10 DOWNTO 0);
	
BEGIN

A:PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
CASE pattern IS
	WHEN  "00001"=>speed<="00000001000";
	WHEN  "00010"=>speed<="00000010000";
    WHEN  "00011"=>speed<="00000011000";
    WHEN  "00100"=>speed<="00000100000";
    WHEN  "00101"=>speed<="00000101000";
	WHEN  OTHERS =>speed<="00000000000";
END CASE;
END IF;
END PROCESS;

B:PROCESS(clk,clken_fcount,m1countreg)
BEGIN
IF(clken_fcount='0') THEN
m1countreg<=m1countreg;
ELSIF clk'event AND clk='1' THEN
IF m1countreg>=HAC THEN
m1countreg<=(OTHERS=>'0');
ELSE
m1countreg<=m1countreg+speed;
END IF;
END IF;
END PROCESS;

C:PROCESS(clk,pm_temp)
BEGIN
IF (pm_temp='1') THEN
m2countreg<=(OTHERS=>'0');
ELSIF clk'event AND clk='1' THEN
IF de_out='1' THEN
m2countreg<=m2countreg+1;
END IF;
END IF;
END PROCESS;
pm_temp<='1' when m2countreg=HAC ELSE '0';
out_r_e<="00000000" when m2countreg<m1countreg ELSE "11111111";
out_g_e<="00000000" when m2countreg<m1countreg ELSE "11111111";
out_b_e<="00000000" when m2countreg<m1countreg ELSE "11111111";
out_r_o<="00000000" when m2countreg<m1countreg ELSE "11111111";
out_g_o<="00000000" when m2countreg<m1countreg ELSE "11111111";
out_b_o<="00000000" when m2countreg<m1countreg ELSE "11111111";


END rtl;