image.fit.qmsg

FPGA控制LCD屏幕显示图像

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 12 16:24:24 2007 " "Info: Processing started: Mon Nov 12 16:24:24 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off cyclic -c image " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off cyclic -c image" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "image EP1C20F324C6 " "Info: Selected device EP1C20F324C6 for design \"image\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C4F324C6 " "Info: Device EP1C4F324C6 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12F324C6 " "Info: Device EP1C12F324C6 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clk Global clock in PIN J4 " "Info: Automatically promoted some destinations of signal \"clk\" to use Global clock in PIN J4" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clk_out " "Info: Destination \"clk_out\" may be non-global or may not use global clock" {  } { { "image.vhd" "" { Text "D:/study/实验室/image1280-50M/image.vhd" 7 -1 0 } }  } 0}  } { { "image.vhd" "" { Text "D:/study/实验室/image1280-50M/image.vhd" 6 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "reduce_nor~1 Global clock " "Info: Automatically promoted signal \"reduce_nor~1\" to use Global clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "reduce_nor~1" } } } } { "D:/study/实验室/image1280-50M/db/image_cmp.qrpt" "" { Report "D:/study/实验室/image1280-50M/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/实验室/image1280-50M/db/cyclic.quartus_db" { Floorplan "D:/study/实验室/image1280-50M/" "" "" { reduce_nor~1 } "NODE_NAME" } "" } } { "D:/study/实验室/image1280-50M/image.fld" "" { Floorplan "D:/study/实验室/image1280-50M/image.fld" "" "" { reduce_nor~1 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "reduce_nor~120 Global clock " "Info: Automatically promoted signal \"reduce_nor~120\" to use Global clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "reduce_nor~120" } } } } { "D:/study/实验室/image1280-50M/db/image_cmp.qrpt" "" { Report "D:/study/实验室/image1280-50M/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/实验室/image1280-50M/db/cyclic.quartus_db" { Floorplan "D:/study/实验室/image1280-50M/" "" "" { reduce_nor~120 } "NODE_NAME" } "" } } { "D:/study/实验室/image1280-50M/image.fld" "" { Floorplan "D:/study/实验室/image1280-50M/image.fld" "" "" { reduce_nor~120 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}