shinning.vhd

FPGA控制LCD屏幕显示图像

LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY shinning IS PORT
( clk    : IN std_logic;
  vcount : IN std_logic_vector(10 DOWNTO 0);
  hcount : IN std_logic_vector(10 DOWNTO 0);
  clken_fcount: IN std_logic;
  pattern: IN std_logic_vector(4  DOWNTO 0);
  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_o   : OUT std_logic_vector(7 DOWNTO 0));

CONSTANT HAC:integer:=512;   -- horizontal active pixels 1448*1151
CONSTANT HFP:integer:=12;     -- horizontal front porch
CONSTANT HSY:integer:=68;     -- horizontal sync width (negative polarity)
CONSTANT HBP:integer:=80;     -- horizontal back porch
CONSTANT HTOT:integer:=672;
CONSTANT VAC:integer:=768;    -- vertical active pixels
CONSTANT VFP:integer:=3;    -- vertical front porch
CONSTANT VSY:integer:=6;      -- vertical sync width (negative polarity)
CONSTANT VBP:integer:=29;     -- vertical back porch
CONSTANT VTOT:integer:=806; -- vertical total lines (in 60 Hz field
END shinning;

ARCHITECTURE rtl OF shinning IS

SIGNAL inter : integer;
SIGNAL color : std_logic;
SIGNAL colorout : std_logic;
SIGNAL vf_temp : std_logic;
SIGNAL scountreg : std_logic_vector(7 DOWNTO 0);
BEGIN

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
CASE pattern IS
	WHEN  "00001"=>inter<=60;
	WHEN  "00010"=>inter<=30;
    WHEN  "00011"=>inter<=20;
    WHEN  "00100"=>inter<=10;
    WHEN  "00101"=>inter<=5;
	WHEN  OTHERS =>inter<=2;
END CASE;
END IF;
END PROCESS;

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
IF vcount=735 AND hcount=HBP+HSY+320 
THEN color<='1';
ELSE color<='0';
END IF;
END IF;
END PROCESS;

PROCESS(clk,vf_temp)
BEGIN
IF(vf_temp='1')THEN
scountreg<=(OTHERS=>'0');
ELSIF clk'event AND clk='1' THEN
IF clken_fcount='1' THEN
scountreg<=scountreg+1;
END IF;
END IF;
END PROCESS;

vf_temp<='1' when scountreg=(inter+inter) ELSE '0';

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
IF scountreg<inter THEN colorout<='0';
ELSIF color='1' THEN colorout<='1';
ELSE colorout<='0';
END IF;
END IF;
END PROCESS;

out_r_e<="00000000" when colorout='0' ELSE "11111111";
out_g_e<="00000000" when colorout='0' ELSE "11111111";
out_b_e<="00000000" when colorout='0' ELSE "11111111";
out_r_o<="00000000" ;
out_g_o<="00000000" ;
out_b_o<="00000000" ;

END rtl;