image.map.summary

FPGA控制LCD屏幕显示图像

Flow Status : Successful - Mon Nov 12 16:24:21 2007
Quartus II Version : 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
Revision Name : image
Top-level Entity Name : image
Family : Cyclone
Device : EP1C20F324C6
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 111
Total pins : 54
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0