📄 pic16f716.h
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/* header file for the MICROCHIP PIC microcontroller
*/
#ifndef __PIC16F716_H
#define __PIC16F716_H
// Special function register definitions
static volatile unsigned char TMR0 @ 0x01;
static volatile unsigned char PCL @ 0x02;
static volatile unsigned char STATUS @ 0x03;
static unsigned char FSR @ 0x04;
static volatile unsigned char PORTA @ 0x05;
static volatile unsigned char PORTB @ 0x06;
static volatile unsigned char PCLATH @ 0x0A;
static volatile unsigned char INTCON @ 0x0B;
static volatile unsigned char PIR1 @ 0x0C;
static volatile unsigned char TMR1L @ 0x0E;
static volatile unsigned char TMR1H @ 0x0F;
static unsigned char T1CON @ 0x10;
static volatile unsigned char TMR2 @ 0x11;
static unsigned char T2CON @ 0x12;
static volatile unsigned char CCPR1L @ 0x15;
static volatile unsigned char CCPR1H @ 0x16;
static volatile unsigned char CCP1CON @ 0x17;
static volatile unsigned char PWM1CON @ 0x18;
static volatile unsigned char ECCPAS @ 0x19;
static volatile unsigned char ADRES @ 0x1E;
static volatile unsigned char ADCON0 @ 0x1F;
static bank1 unsigned char OPTION @ 0x81;
static volatile bank1 unsigned char TRISA @ 0x85;
static volatile bank1 unsigned char TRISB @ 0x86;
static bank1 unsigned char PIE1 @ 0x8C;
static volatile bank1 unsigned char PCON @ 0x8E;
static bank1 unsigned char PR2 @ 0x92;
static bank1 unsigned char ADCON1 @ 0x9F;
/* Definitions for STATUS register */
static volatile bit CARRY @ ((unsigned)&STATUS*8)+0;
static volatile bit DC @ ((unsigned)&STATUS*8)+1;
static volatile bit ZERO @ ((unsigned)&STATUS*8)+2;
static volatile bit PD @ ((unsigned)&STATUS*8)+3;
static volatile bit TO @ ((unsigned)&STATUS*8)+4;
static bit RP0 @ ((unsigned)&STATUS*8)+5;
static bit RP1 @ ((unsigned)&STATUS*8)+6;
static bit IRP @ ((unsigned)&STATUS*8)+7;
/* Definitions for PORTA register */
static volatile bit RA0 @ ((unsigned)&PORTA*8)+0;
static volatile bit RA1 @ ((unsigned)&PORTA*8)+1;
static volatile bit RA2 @ ((unsigned)&PORTA*8)+2;
static volatile bit RA3 @ ((unsigned)&PORTA*8)+3;
static volatile bit RA4 @ ((unsigned)&PORTA*8)+4;
/* Definitions for PORTB register */
static volatile bit RB0 @ ((unsigned)&PORTB*8)+0;
static volatile bit RB1 @ ((unsigned)&PORTB*8)+1;
static volatile bit RB2 @ ((unsigned)&PORTB*8)+2;
static volatile bit RB3 @ ((unsigned)&PORTB*8)+3;
static volatile bit RB4 @ ((unsigned)&PORTB*8)+4;
static volatile bit RB5 @ ((unsigned)&PORTB*8)+5;
static volatile bit RB6 @ ((unsigned)&PORTB*8)+6;
static volatile bit RB7 @ ((unsigned)&PORTB*8)+7;
/* Definitions for INTCON register */
static volatile bit RBIF @ ((unsigned)&INTCON*8)+0;
static volatile bit INTF @ ((unsigned)&INTCON*8)+1;
static volatile bit T0IF @ ((unsigned)&INTCON*8)+2;
static bit RBIE @ ((unsigned)&INTCON*8)+3;
static bit INTE @ ((unsigned)&INTCON*8)+4;
static bit T0IE @ ((unsigned)&INTCON*8)+5;
static bit PEIE @ ((unsigned)&INTCON*8)+6;
static bit GIE @ ((unsigned)&INTCON*8)+7;
/* Definitions for PIR1 register */
static volatile bit TMR1IF @ ((unsigned)&PIR1*8)+0;
static volatile bit TMR2IF @ ((unsigned)&PIR1*8)+1;
static volatile bit CCP1IF @ ((unsigned)&PIR1*8)+2;
static volatile bit ADIF @ ((unsigned)&PIR1*8)+6;
/* Definitions for T1CON register */
static bit TMR1ON @ ((unsigned)&T1CON*8)+0;
static bit TMR1CS @ ((unsigned)&T1CON*8)+1;
static bit T1SYNC @ ((unsigned)&T1CON*8)+2;
static bit T1OSCEN @ ((unsigned)&T1CON*8)+3;
static bit T1CKPS0 @ ((unsigned)&T1CON*8)+4;
static bit T1CKPS1 @ ((unsigned)&T1CON*8)+5;
/* Definitions for T2CON register */
static bit T2CKPS0 @ ((unsigned)&T2CON*8)+0;
static bit T2CKPS1 @ ((unsigned)&T2CON*8)+1;
static bit TMR2ON @ ((unsigned)&T2CON*8)+2;
static bit TOUTPS0 @ ((unsigned)&T2CON*8)+3;
static bit TOUTPS1 @ ((unsigned)&T2CON*8)+4;
static bit TOUTPS2 @ ((unsigned)&T2CON*8)+5;
static bit TOUTPS3 @ ((unsigned)&T2CON*8)+6;
/* Definitions for CCP1CON register */
static bit CCP1M0 @ ((unsigned)&CCP1CON*8)+0;
static bit CCP1M1 @ ((unsigned)&CCP1CON*8)+1;
static bit CCP1M2 @ ((unsigned)&CCP1CON*8)+2;
static bit CCP1M3 @ ((unsigned)&CCP1CON*8)+3;
static bit DC1B0 @ ((unsigned)&CCP1CON*8)+4;
static bit DC1B1 @ ((unsigned)&CCP1CON*8)+5;
static bit P1M0 @ ((unsigned)&CCP1CON*8)+6;
static bit P1M1 @ ((unsigned)&CCP1CON*8)+7;
/* Definitions for PWM1CON register */
static volatile bit PDC0 @ ((unsigned)&PWM1CON*8)+0;
static volatile bit PDC1 @ ((unsigned)&PWM1CON*8)+1;
static volatile bit PDC2 @ ((unsigned)&PWM1CON*8)+2;
static volatile bit PDC3 @ ((unsigned)&PWM1CON*8)+3;
static volatile bit PDC4 @ ((unsigned)&PWM1CON*8)+4;
static volatile bit PDC5 @ ((unsigned)&PWM1CON*8)+5;
static volatile bit PDC6 @ ((unsigned)&PWM1CON*8)+6;
static volatile bit PRSEN @ ((unsigned)&PWM1CON*8)+7;
/* Definitions for ECCPAS register */
static bit PSSBD0 @ ((unsigned)&ECCPAS*8)+0;
static bit PSSBD1 @ ((unsigned)&ECCPAS*8)+1;
static bit PSSAC0 @ ((unsigned)&ECCPAS*8)+2;
static bit PSSAC1 @ ((unsigned)&ECCPAS*8)+3;
static bit ECCPAS0 @ ((unsigned)&ECCPAS*8)+4;
static bit ECCPAS2 @ ((unsigned)&ECCPAS*8)+6;
static volatile bit ECCPASE @ ((unsigned)&ECCPAS*8)+7;
/* Definitions for ADCON0 register */
static bit ADON @ ((unsigned)&ADCON0*8)+0;
static volatile bit GODONE @ ((unsigned)&ADCON0*8)+2;
static bit CHS0 @ ((unsigned)&ADCON0*8)+3;
static bit CHS1 @ ((unsigned)&ADCON0*8)+4;
static bit CHS2 @ ((unsigned)&ADCON0*8)+5;
static bit ADCS0 @ ((unsigned)&ADCON0*8)+6;
static bit ADCS1 @ ((unsigned)&ADCON0*8)+7;
/* Definitions for OPTION register */
static bank1 bit PS0 @ ((unsigned)&OPTION*8)+0;
static bank1 bit PS1 @ ((unsigned)&OPTION*8)+1;
static bank1 bit PS2 @ ((unsigned)&OPTION*8)+2;
static bank1 bit PSA @ ((unsigned)&OPTION*8)+3;
static bank1 bit T0SE @ ((unsigned)&OPTION*8)+4;
static bank1 bit T0CS @ ((unsigned)&OPTION*8)+5;
static bank1 bit INTEDG @ ((unsigned)&OPTION*8)+6;
static bank1 bit RBPU @ ((unsigned)&OPTION*8)+7;
/* Definitions for TRISA register */
static volatile bank1 bit TRISA0 @ ((unsigned)&TRISA*8)+0;
static volatile bank1 bit TRISA1 @ ((unsigned)&TRISA*8)+1;
static volatile bank1 bit TRISA2 @ ((unsigned)&TRISA*8)+2;
static volatile bank1 bit TRISA3 @ ((unsigned)&TRISA*8)+3;
static volatile bank1 bit TRISA4 @ ((unsigned)&TRISA*8)+4;
/* Definitions for TRISB register */
static volatile bank1 bit TRISB0 @ ((unsigned)&TRISB*8)+0;
static volatile bank1 bit TRISB1 @ ((unsigned)&TRISB*8)+1;
static volatile bank1 bit TRISB2 @ ((unsigned)&TRISB*8)+2;
static volatile bank1 bit TRISB3 @ ((unsigned)&TRISB*8)+3;
static volatile bank1 bit TRISB4 @ ((unsigned)&TRISB*8)+4;
static volatile bank1 bit TRISB5 @ ((unsigned)&TRISB*8)+5;
static volatile bank1 bit TRISB6 @ ((unsigned)&TRISB*8)+6;
static volatile bank1 bit TRISB7 @ ((unsigned)&TRISB*8)+7;
/* Definitions for PIE1 register */
static bank1 bit TMR1IE @ ((unsigned)&PIE1*8)+0;
static bank1 bit TMR2IE @ ((unsigned)&PIE1*8)+1;
static bank1 bit CCP1IE @ ((unsigned)&PIE1*8)+2;
static bank1 bit ADIE @ ((unsigned)&PIE1*8)+6;
/* Definitions for PCON register */
static volatile bank1 bit BOR @ ((unsigned)&PCON*8)+0;
static volatile bank1 bit POR @ ((unsigned)&PCON*8)+1;
/* Definitions for ADCON1 register */
static bank1 bit PCFG0 @ ((unsigned)&ADCON1*8)+0;
static bank1 bit PCFG1 @ ((unsigned)&ADCON1*8)+1;
static bank1 bit PCFG2 @ ((unsigned)&ADCON1*8)+2;
// Configuration Mask Definitions
#define CONFIG_ADDR 0x2007
// Protection of flash memory
#define PROTECT 0x1FFF
#define UNPROTECT 0x3FFF
// Brown-Out reset enable
#define BORV25 0x3F7F
#define BORV40 0x3FFF
#define BORON 0x3FFF
#define BORDIS 0x3FBF
// Power up timer enable
#define PWRTEN 0x3FF7
#define PWRTDIS 0x3FFF
// Watchdog timer enable
#define WDTEN 0x3FFF
#define WDTDIS 0x3FFB
// Oscillator configurations
#define RC 0x3FFF
#define HS 0x3FFE
#define XT 0x3FFD
#define LP 0x3FFC
#endif
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