📄 class.ptf
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## This class.ptf file built by Component Editor# 2007.01.16.21:42:58## DO NOT MODIFY THIS FILE# If you hand-modify this file you will likely# interfere with Component Editor's ability to# read and edit it. And then Component Editor# will overwrite your changes anyway. So, for# the very best results, just relax and# DO NOT MODIFY THIS FILE#CLASS gpio{ CB_GENERATOR { HDL_FILES { FILE { use_in_simulation = "1"; use_in_synthesis = "1"; type = "verilog"; filepath = "hdl/gpio.v"; } } top_module_name = "gpio.v:gpio"; emit_system_h = "0"; LIBRARIES { } } MODULE_DEFAULTS global_signals { class = "gpio"; class_version = "1.0"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Has_Clock = "1"; Top_Level_Ports_Are_Enumerated = "1"; } COMPONENT_BUILDER { GLS_SETTINGS { } } PORT_WIRING { PORT clk { width = "1"; width_expression = ""; direction = "input"; type = "clk"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT reset_n { width = "1"; width_expression = ""; direction = "input"; type = "reset_n"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } } WIZARD_SCRIPT_ARGUMENTS { hdl_parameters { width = "2"; } } SIMULATION { DISPLAY { } } SLAVE avalon_slave_0 { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Group = "1"; Has_Clock = "0"; Address_Width = "4"; Address_Alignment = "native"; Data_Width = "8"; Has_Base_Address = "1"; Has_IRQ = "0"; Setup_Time = "0cycles"; Hold_Time = "0cycles"; Read_Wait_States = "0cycles"; Write_Wait_States = "0cycles"; Read_Latency = "0"; Maximum_Pending_Read_Transactions = "0"; Active_CS_Through_Read_Latency = "0"; Is_Printable_Device = "0"; Is_Memory_Device = "0"; Is_Readable = "0"; Is_Writable = "1"; Minimum_Uninterrupted_Run_Length = "1"; } COMPONENT_BUILDER { AVS_SETTINGS { Setup_Value = "0"; Read_Wait_Value = "0"; Write_Wait_Value = "0"; Hold_Value = "0"; Timing_Units = "cycles"; Read_Latency_Value = "0"; Minimum_Arbitration_Shares = "1"; Active_CS_Through_Read_Latency = "0"; Max_Pending_Read_Transactions_Value = "1"; Address_Alignment = "native"; Is_Printable_Device = "0"; Interleave_Bursts = "0"; interface_name = "Avalon Slave"; external_wait = "0"; Is_Memory_Device = "0"; } } PORT_WIRING { PORT readdata { width = "1"; width_expression = ""; direction = "output"; type = "readdata"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT bidir_port { width = "-1"; width_expression = "(WIDTH-1) - (0) + 1"; direction = "inout"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT address { width = "4"; width_expression = ""; direction = "input"; type = "address"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT write_n { width = "1"; width_expression = ""; direction = "input"; type = "write_n"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT writedata { width = "2"; width_expression = ""; direction = "input"; type = "writedata"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } } } } USER_INTERFACE { USER_LABELS { name = "gpio"; technology = "Other"; } WIZARD_UI the_wizard_ui { title = "gpio - {{ $MOD }}"; CONTEXT { H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters"; M = ""; SBI_global_signals = "SYSTEM_BUILDER_INFO"; SBI_avalon_slave_0 = "SLAVE avalon_slave_0/SYSTEM_BUILDER_INFO"; # The following signals have parameterized widths: PORT_bidir_port = "SLAVE avalon_slave_0/PORT_WIRING/PORT bidir_port"; } PAGES main { PAGE 1 { align = "left"; title = "<b>gpio 1.0</b> Settings"; layout = "vertical"; TEXT { title = "Built on: 2007.01.16.21:42:58"; } TEXT { title = "Class name: gpio"; } TEXT { title = "Class version: 1.0"; } TEXT { title = "Component name: gpio"; } TEXT { title = "Component Group: Other"; } GROUP parameters { title = "Parameters"; layout = "form"; align = "left"; EDIT e1 { id = "WIDTH"; editable = "1"; title = "WIDTH:"; columns = "40"; tooltip = "default value: 2"; DATA { $H/width = "$"; } q = "'"; warning = "{{ if(!(regexp('ugly_'+$H/width,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/width,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/width,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/width,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/width,'ugly_-?[0-9]+')))'WIDTH must be numeric constant, not '+$H/width; }}"; } } GROUP variable_port_widths { # This group is for display only, to preview parameterized port widths title = "Parameterized Signal Widths"; layout = "form"; align = "left"; EDIT bidir_port_width { id = "bidir_port_width"; editable = "0"; title = "bidir_port[(WIDTH-1) - (0) + 1]:"; tooltip = "<b>bidir_port[(WIDTH-1) - (0) + 1]</b><br> direction: inout<br> signal type: export"; # This expression should emulate the HDL, and assign the port width dummy = "{{ $PORT_bidir_port/width = (int(( ( $H/width ) -1) - (0) + 1-1) - int(0) + 1); }}"; DATA { # The EDIT field is noneditable, so this just reads the current width. $PORT_bidir_port/width = "$"; } warning = "{{ if($PORT_bidir_port/width <= 0)('width of bidir_port must be greater than zero' ) }}"; } } } } } } SOPC_Builder_Version = "6.10"; COMPONENT_BUILDER { HDL_PARAMETERS { # generated by CBDocument.getParameterContainer # used only by Component Editor HDL_PARAMETER width { parameter_name = "WIDTH"; type = "integer"; default_value = "2"; editable = "1"; tooltip = ""; } } SW_FILES { } built_on = "2007.01.16.21:42:58"; CACHED_HDL_INFO { # cached hdl info, emitted by CBFrameRealtime.getDocumentCachedHDLInfoSection # used only by Component Builder FILE gpio.v { file_mod = "Tue Jan 16 21:17:50 CST 2007"; quartus_map_start = "Tue Jan 16 21:22:19 CST 2007"; quartus_map_finished = "Tue Jan 16 21:22:42 CST 2007"; #found 1 valid modules WRAPPER gpio { CLASS gpio { CB_GENERATOR { HDL_FILES { FILE { use_in_simulation = "1"; use_in_synthesis = "1"; type = ""; filepath = "/home/thomas/new2/gpio/gpio.v"; } } top_module_name = "gpio"; emit_system_h = "0"; } MODULE_DEFAULTS global_signals { class = "gpio"; class_version = "1.0"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; } SLAVE avalon_slave_0 { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; } PORT_WIRING { PORT readdata { width = "1"; width_expression = ""; direction = "output"; type = "readdata"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT bidir_port { width = "-1"; width_expression = "(WIDTH-1) - (0) + 1"; direction = "inout"; type = "export"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT address { width = "4"; width_expression = ""; direction = "input"; type = "address"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT write_n { width = "1"; width_expression = ""; direction = "input"; type = "write_n"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT writedata { width = "2"; width_expression = ""; direction = "input"; type = "writedata"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } } } PORT_WIRING { PORT clk { width = "1"; width_expression = ""; direction = "input"; type = "clk"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } PORT reset_n { width = "1"; width_expression = ""; direction = "input"; type = "reset_n"; is_shared = "0"; vhdl_record_name = ""; vhdl_record_type = ""; } } } USER_INTERFACE { USER_LABELS { name = "gpio"; technology = "imported components"; } } SOPC_Builder_Version = "0.0"; COMPONENT_BUILDER { HDL_PARAMETERS { # generated by CBDocument.getParameterContainer # used only by Component Editor HDL_PARAMETER width { parameter_name = "WIDTH"; type = "integer"; default_value = "2"; editable = "1"; tooltip = ""; } } } } } } } } ASSOCIATED_FILES { Add_Program = "the_wizard_ui"; Edit_Program = "the_wizard_ui"; Generator_Program = "cb_generator.pl"; }}
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