📄 phantomeppsrlapi.h
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//////////////////////////////////////////////////////////////////
//
// PhantomEPPSRLAPI.h - Header file
//
// This file was generated using the RTX Device Driver Wizard.
//
//////////////////////////////////////////////////////////////////
#ifndef _PhantomEPP_SRL_API_HEADER_
#define _PhantomEPP_SRL_API_HEADER_
#include <rtapi.h>
#include "RtDriver.h"
#include "PhantomIoCtl.h"
//
// General definitions
//
#define MAX_NAME 128
#define MAX_DESC 128
#define MAX_NAME_DISPLAY 22
//
// Data definitions for Parallel driver
//
#define DISABLE_INTERRUPTS _asm cli
#define ENABLE_INTERRUPTS _asm sti
#define EPP_PORT 0x378 //port address for EPP
#define EPP_IRQ 0x7 //EPP interrupt request level
#define EPP_IO_RANGE 8 //8 registers,including scratch
#define IST_PRIORITY RT_PRIORITY_MAX
#define RING_BUFFER_SIZE 8192 //default size of a ring buffer
#define FIFO_SIZE 14
//
// Define EPP register offsets
//
#define UART_DATA_REG 0
#define UART_STATUS_REG 1
#define UART_CTRL_REG 2
#define UART_ADDR_REG 3
#define UART_DATA0_REG 4
#define UART_DATA1_REG 5
#define UART_DATA2_REG 6
#define UART_DATA3_REG 7
//
// Define UART interrupt types
//
#define IIR_EPP_STATUS 0x00
#define IIR_NO_INT_PENDING 0x01
#define IIR_XMIT_HOLDING_EMPTY 0x02
#define IIR_RECEIVED_DATA_READY 0x04
#define IIR_RECEIVER_LINE_STATUS 0x06
#define IIR_RECEIVE_DATA_TIMEOUT 0x0c
#define IIR_MASK 0xff
//
// Define bit masks for LSR
//
#define LSR_DATA_READY 0x80
#define LSR_OVERRUN_ERROR 0x02
#define LSR_PARITY_ERROR 0x04
#define LSR_FRAMING_ERROR 0x08
#define LSR_BREAK 0x10
#define LSR_EMPTY_XMIT_HOLDING_REG 0x20
#define LSR_TRANSMITTER_EMPTY 0x40
#define LSR_FIFO_ERROR 0x80
//
// Define bit masks for status register
//
#define STATUS_WAIT 0x00
#define STATUS_INTR 0x00
#define STATUS_USER1 0x00
#define STATUS_USER2 0x00
#define STATUS_USER3 0x00
#define STATUS_TMOUT 0x00
//
// Define bit masks for status register
//
#define CTRL_DIR 0x00
#define CTRL_IRQEN 0x00
#define CTRL_ASTRB 0x00
#define CTRL_INIT 0x00
#define CTRL_DSTRB 0x00
#define CTRL_WRITE 0x00
//
// Defines for Parameters
//
#define PORT_PARITY_NONE 0x00
//
// Define the API return codes
//
#define ERROR_NORMAL 0 // normal return
#define ERROR_RECEIVE_BUFFER_OVERFLOW 1 //receive ring buffer full
#define ERROR_TRANSMIT_BUFFER_OVERFLOW 2 //transmit ring buffer full
#define ERROR_DEVICE_OPEN 3 //device already open
#define ERROR_INVALID_DEVICE 6 //invalid or unsupport port
#define ERROR_PORT_IO_FAILURE 7 //Enable port i/o failed
#define ERROR_CONNECT_INTERRUPT_FAILED 8 //unable to connect to interrupt
#define ERROR_PORT_NOT_OPEN 9 //com port not yet open
#define ERROR_PORT_UNSUPPORTED_INTERRUPT 10 //ist received an unsupported inetrrupt
#define ERROR_PORT_UNSOLICITED_INTERRUPT 11 //ist received an unsolicited inetrruptv
#define RESUME_THREAD_FAILED 0XFFFFFFFF
//
// Define a Ring Buffer
//
typedef struct
{
BYTE buffer[RING_BUFFER_SIZE]; //pointer to a character buffer
WORD count; //count of characters in buffer
WORD nextSlotOut; //pointer to next input slot
WORD nextSlotIn; //pointer to last character read
}RINGBUFFER;
//
// Define a Universal Asynchronous Receiver/Transmitter (UART) Control Block
//
typedef VOID (RTFCNDCL *RoutineDPC)(PVOID context);
typedef struct
{
PUCHAR baseAddress; // base port address
HANDLE istHandle; // handle to Rt interrupt routine
WORD intVector; // interrupt vector
WORD irq; // IRQ level
RINGBUFFER *inBuffer; // pointer to input ringbuffer
RINGBUFFER *outBuffer; // pointer to output ringbuffer
BYTE fifoMask; // FIFO register mask
BYTE fifoSize; // size of FIFO..default = 14
BYTE parity; // parity odd/even/none
BYTE stopBits; // 0 1 or 2 stop bits
BYTE receiveISTActive:1; // receive interrupt pending
BYTE transmitISTActive:1; // transmit Interrupt pending
BYTE wordSize; // word size..5 - 8 bits
BYTE baudRate; // configured baud rate
BYTE flowControl; // flow control
WORD lastError; // last reported error
WORD errorCount; // count of errors
///////////////////////////////////////////////////////////////////////
ULONG m_DeviceNumber;
ULONG m_DeviceIndex;
LONG m_nFileCount;
HANDLE m_SignalEventHandle;
HANDLE m_SignalEventObject;
ULONG m_SignalEventCount;
BOOLEAN m_SoftwareTimerEnabled;
HANDLE m_SoftwareTimer;
RoutineDPC m_SoftwareTimerDPC;
LARGE_INTEGER m_SoftwareTimerDueTime;
LARGE_INTEGER m_SoftwareTimerInterval;
BOOLEAN m_ParPortAllocated;
BOOLEAN m_ParPortInterruptAllocated;
BOOLEAN m_PPT_BYTE_PRESENT;
BOOLEAN m_PPT_1284_3_PRESENT;
BOOLEAN m_PPT_ECP_PRESENT;
BOOLEAN m_PPT_EPP_32_PRESENT;
BOOLEAN m_PPT_EPP_PRESENT;
BOOLEAN m_RegistryEnableInterruptsChanged;
UCHAR m_ChannelMask;
UCHAR m_ReadBuffers[PHANTOM_MAX_CHANNELS][PHANTOM_MAXBLOCKSIZE];
UCHAR m_WriteBuffers[PHANTOM_MAX_CHANNELS][PHANTOM_MAXBLOCKSIZE];
UCHAR m_PrevWatchdogOut[PHANTOM_MAX_CHANNELS];
UCHAR m_WatchdogErrorCount[PHANTOM_MAX_CHANNELS];
BOOLEAN m_EnableSoftwareWatchdog;
HANDLE m_TimeoutTimer;
RoutineDPC m_TimeoutDPC;
HANDLE m_TimeoutEvent;
BOOLEAN m_TimeoutCount;
BOOLEAN m_IsClose;
}UCB;
//
// Define a structure for a baud rate table
//
typedef struct
{
DWORD rate; // the actual rate
BYTE DLHigh; // divisor latch high
BYTE DLLow; // divisor latch low
}BAUDRATE;
//
// Define a FIFO structure
//
typedef struct
{
BYTE size;
BYTE mask;
}FIFO;
//////////////////////////////////////////////////////////////////////////////////////
#define KDPRINTTAG "PHANTOMEPP:"
#define DEVICE_NAME_BUFFER_SIZE (128)
#define SOFTWARE_WATCHDOG_TIMEOUT (100000) // 10 ms
// For error reporting in the system event log
#define PHANTOMEPP_ERROR_VALUE_BASE 26000
#define NUM_PING_TESTS (10)
//
// Register offsets:
//
#define STATUS_REGISTER (1)
#define CONTROL_REGISTER (2)
#define ADDRESS_REGISTER (3)
#define DATA_REGISTER (4)
#define ECR_REGISTER (0x402)
#define ECP_FIFO (0x400)
#define ECR_CONFIG (0x401)
//
// Status register bits:
//
enum EppStatusBits
{
EPP_STATUS_TIMEOUT = 0,
EPP_STATUS_RESERVED1 = 1,
EPP_STATUS_IRQNOT = 2,
EPP_STATUS_nERROR = 3,
EPP_STATUS_SELECT = 4,
EPP_STATUS_PAPEREND = 5,
EPP_STATUS_nACK = 6,
EPP_STATUS_nBUSY = 7
};
//
// Define access macros for registers. Each macro takes
// a pointer the PortBase as an argument
//
#define ReadStatus( _PortBase_) (RtReadPortUchar(_PortBase_ + STATUS_REGISTER))
#define WriteStatus(_PortBase_,bData ) (RtWritePortUchar(_PortBase_ + STATUS_REGISTER, bData ))
#define ReadControl( _PortBase_) (RtReadPortUchar( _PortBase_ + CONTROL_REGISTER))
#define WriteControl(_PortBase_, bData ) (RtWritePortUchar(_PortBase_ + CONTROL_REGISTER, bData ))
#define WriteAddress(_PortBase_, bData ) (RtWritePortUchar(_PortBase_ + ADDRESS_REGISTER, bData ))
#define ReadByte(_PortBase_) (RtReadPortUchar(_PortBase_ + DATA_REGISTER))
#define ReadBlock(_PortBase_,pBuffer,bCount ) (RtReadPortBufferUchar(_PortBase_ + DATA_REGISTER,pBuffer,bCount ))
#define WriteByte(_PortBase_, bData) (RtWritePortUchar(_PortBase_ + DATA_REGISTER, bData ))
#define WriteBlock(_PortBase_,pBuffer,bCount ) (RtWritePortBufferUchar(_PortBase_ + DATA_REGISTER,pBuffer,bCount ))
#define ReadECR( _PortBase_) (RtReadPortUchar(_PortBase_ + ECR_REGISTER))
#define WriteECR(_PortBase_, bData ) (RtWritePortUchar(_PortBase_ + ECR_REGISTER, bData ))
#define TEST_BIT(x, b) (((x) & (1 << (b))) != 0)
#endif //_PhantomEPP_SRL_API_HEADER_
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