int.s

test file nucleus source

    LDR     r3,Module_FIQ_Base              ; Get FIQ base register address
    STR     r4,[r3,#INT_CLEAR_OFFSET]       ; Disable all lower priority 
                                            ; interrupts
    ; End Board Specific Section

    ; Load the branch address from the vector table

    LDR     r3,=INT_FIQ_Vectors             ; Get FIQ vector table address
    MOV     r2, r0, LSL #2                  ; Multiply vector by 4 to get 
                                            ; offset into table
    ADD     r3, r3, r2                      ; Adjust vector table address to 
                                            ; correct offset
    LDR     r2, [r3,#0]                     ; Load branch address from vector 
                                            ; table
    MOV     PC, r2                          ; Jump to correct branch location 
                                            ; based on vector table
    ELSE

    B       INT_FIQ

    ENDIF   ; NU_FIQ_SUPPORT


;************************************************************************
;*
;*  FUNCTION
;*
;*      INT_Timer_Interrupt
;*
;*  DESCRIPTION
;*
;*      This assembly function is responsible for handling any target
;*      specific aspects of the Nucelus PLUS timer interrupt.  This
;*      includes saving any necessary registers, clearing the
;*      interrupt at the source, and calling the timer interrupt
;*      service routine TMT_Timer_Interrupt.
;*
;*  CALLED BY
;*
;*      INT_IRQ / INT_FIQ
;*
;*  CALLS
;*
;*      TMT_Timer_Interrupt
;*
;*  INPUTS
;*
;*      r0  -   vector number
;*
;*  OUTPUTS
;*
;*      None
;*
;*  REGISTERS MODIFIED
;*
;*      None
;*
;*  HISTORY
;*
;*      NAME            DATE            REMARKS
;*
;*      C. March     07/15/2003      Released Version 1.14.9
;************************************************************************
;static VOID    INT_Timer_Interrupt

INT_Timer_Interrupt

    ; Lock-out all interrupts

    MRS     r0,CPSR                         ; Pickup current CPSR
    ORR     r0,r0,#LOCKOUT                  ; Lock-out interrupts
    MSR     CPSR_cxsf,r0                    ; Setup the new CPSR

    ; ************ START TARGET SPECIFIC SECTION **************

    ; Clear the timer interrupt

    LDR     r1,=TIMER1_BASE                 ; Get timer base
    MOV     r2,#TIMER_CLEAR_VALUE           ; Get clear value
    STRB    r2,[r1,#TIMER_CLEAR_OFFSET]     ; Clear timer interrupt

    ; ************ END TARGET SPECIFIC SECTION **************

    ; Call the timer interrupt handler

    B       TMT_Timer_Interrupt


;************************************************************************
;*
;*  FUNCTION
;*
;*      INT_HW_Memory_Initialize
;*
;*  DESCRIPTION
;*
;*      This assembly function sets-up all memory for correct target 
;*      operation.  This includes setting the SDRAM Controller, 
;*      Bus Control Registers, Chip Selects, Re-mapping memory, etc.  
;*      Some parts of this file may not be necessary to execute when 
;*      running from RAM (if already initialized by debugger or monitor).
;*
;*  CALLED BY
;*
;*      INT_Initialize
;*
;*  CALLS
;*
;*      None
;*
;*  INPUTS
;*
;*      None
;*
;*  OUTPUTS
;*
;*      None
;*
;*  REGISTERS MODIFIED
;*
;*      None
;*
;*  HISTORY
;*
;*      NAME            DATE            REMARKS
;*
;*      C. March     07/15/2003      Released Version 1.14.9
;************************************************************************
; static VOID   INT_HW_Memory_Initialize(VOID)

INT_HW_Memory_Initialize

    IF  NU_ROM_SUPPORT

    ; Get the header base (r1) and remap memory
    ; Get the base for the Core module registers 

    LDR     r1, =HDR_CNTRL_BASE

    ; Set the re-map bit so memory accesses to 0x00000000 - 0x0003FFFF are sent
    ; to the Core Module SDRAM

    LDR     r2, [r1, #HDR_CONTROL]          ; Get the current register value
    ORR     r2, r2, #INTEGRATOR_REMAP       ; Set the remap bit to ON
    STR     r2, [r1, #HDR_CONTROL]          ; Store the new register value

    ; Perform some card specific intialization
    
    IF (NU_940T_SUPPORT :LOR: NU_966E_SUPPORT)

    ; Set nFastBus and asynchronous clock bits in CP15 register 1

    MRC   p15, 0, r0, c1, c0, 0
    ORR   r0, r0, #0xC0000000
    MCR   p15, 0, r0, c1, c0, 0

    ENDIF

    IF NU_720T_SUPPORT

    ; Ensure Fastbus bit in HDR_CTRL is cleared.

    LDR     r0, [r1, #HDR_CONTROL]
    BIC     r0, r0, #INTEGRATOR_FASTBUS
    STR     r0, [r1, #HDR_CONTROL]

    ENDIF


    ; Wait for the SDRAM SPD to be ready to read
    ; Counter used to allow RAM SPD to become available

    MOV     r2, #0x10000

    ; Get SDRAM control register value

INT_RAM_SPD_Loop
    LDR     r0, [r1, #HDR_SDRAM_OFFSET]

    TST     r0, #0x05                       ; Check if bit 5 set (SPD data ready)
    BNE     INT_RAM_SPD_Rdy                 ; If bit set, branch

    SUBS    r2, r2, #1                      ; Decrement the counter
    BGT     INT_RAM_SPD_Loop                ; Try again 

    ; Get the SDRAM size (cannot be 0 or > 256 MB)

INT_RAM_SPD_Rdy

    ; Get address of SDRAM SPD memory base

    LDR     r0, =(HDR_CNTRL_BASE + HDR_SPD_OFFSET)

    ; Calculate the SDRAM size

    LDRB    r2, [r0, #31]                   ; Get Module Bank Density
    MOV     r2, r2, LSL #2                  ; Multiply by 4
    LDRB    r3, [r0, #5]                    ; Get Number of Banks
    MULS    r2, r3, r2                      ; Multiple together to get size in MBytes

    BEQ     INT_RAM_Init_Fail               ; If zero then goto fail

    CMP     r2, #256                        ; If greater than 256 MB, fail
    BGT     INT_RAM_Init_Fail

    ; Convert MBytes to value to write to MEMSIZE
    ; in HDR SDRAM control register

    BLT     INT_Check_128MB
    LDR     r3, = SDRAM_256MB
    B       INT_SDRAM_Size_Done

INT_Check_128MB
    CMP     r2, #128
    BLT     INT_Check_64MB

    LDR     r3, = SDRAM_128MB
    B       INT_SDRAM_Size_Done

INT_Check_64MB
    CMP     r2, #64
    BLT     INT_Check_32MB

    LDR     r3, = SDRAM_64MB
    B       INT_SDRAM_Size_Done

INT_Check_32MB
    CMP     r2, #32
    BLT     INT_Set_16MB

    LDR     r3, = SDRAM_32MB
    B       INT_SDRAM_Size_Done

INT_Set_16MB
    LDR     r3, = SDRAM_16MB

    ; Update the SDRAM register with the found
    ; memory values

INT_SDRAM_Size_Done
    
    ; Get the contents of the SDRAM control register

    LDR     r2, [r1, #HDR_SDRAM_OFFSET]
    AND     r2, r2, #0x03                   ; Clear everything but the CAS latency
    ORR     r2, r2, r3                      ; Merge our SDRAM size into the register value

    ; Get the number of rows from the SPD

    LDRB    r0, [r1, #(HDR_SPD_OFFSET + 3)]
    AND     r0, r0, #0x0F                   ; Only want bottom 4 bits
    ORR     r2, r2, r0, LSL #8              ; Merge into the register value

    ; Get the number of columns from the SPD

    LDRB    r0, [r1, #(HDR_SPD_OFFSET + 4)]
    AND     r0, r0, #0x0F                   ; Only want bottom 4 bits
    ORR     r2, r2, r0, LSL #12             ; Merge into the register value

    ; Get the number of banks from the SPD

    LDRB    r0, [r1, #(HDR_SPD_OFFSET + 5)]
    AND     r0, r0, #0x0F                   ; Only want bottom 4 bits
    ORR     r2, r2, r0, LSL #16             ; Merge into the register value

    ; Write the new value to the SDRAM control register

    STR     r2, [r1, #HDR_SDRAM_OFFSET]

    B       INT_End_Mem_Init

INT_RAM_Init_Fail

    ; Get the contents of the SDRAM control register

    LDR     r2, [r1, #HDR_SDRAM_OFFSET]
    AND     r2, r2, #0x03                   ; Clear everything but the CAS latency
    ORR     r2, r2, #(7 << 2)               ; Set MEMSIZE to a invalid value.

    ; Write the new value to the SDRAM control register

    STR     r2, [r1, #HDR_SDRAM_OFFSET]

    ; Return to caller

INT_End_Mem_Init

    ENDIF   ; NU_ROM_SUPPORT

    BX      lr
   

;************************************************************************
;*
;*  FUNCTION
;*
;*      INT_Target_Initialize
;*
;*  DESCRIPTION
;*
;*      This assembly function sets-up all processor / target specific
;*      items required for target operation.  This includes setting the
;*      SDRAM Controller, Bus Control Registers, Chip Selects, Caching,
;*      System Registers, Re-mapping memory, etc.  Some parts of this
;*      file may not be necessary to execute when running from RAM
;*      (if already initialized by debugger or monitor).
;*
;*  CALLED BY
;*
;*      INT_Initialize
;*
;*  CALLS
;*
;*      None
;*
;*  INPUTS
;*
;*      None
;*
;*  OUTPUTS
;*
;*      None
;*
;*  REGISTERS MODIFIED
;*
;*      None
;*
;*  HISTORY
;*
;*      NAME            DATE            REMARKS
;*
;*      C. March     07/15/2003      Released Version 1.14.9
;************************************************************************
; static VOID   INT_Target_Initialize(VOID)

INT_Target_Initialize

    ; Save working register on stack

    STMDB   sp!,{lr}

    ; ************ START TARGET SPECIFIC SECTION **************

    IF NU_MMU_MODE                          ; disable MMU

    MRC     p15,0,r0,c1,c0,0                ; read control register into r0
    BIC     r0,r0,#(0x1 <<12)               ; Disable I Cache
    BIC     r0,r0,#(0x1 <<2)                ; Disable D Cache
    BIC     r0,r0,#0x1                      ; clear MMU bit
    MCR     p15,0,r0,c1,c0,0                ; write value back
                                            
    MOV     r0,#0                           
    MCR     p15,0,r0,c7,c7,0                ; Flush cache
                                            
    MOV     r0,#0                           
    MCR     p15,0,r0,c8,c7,0                ; invalidate TLBs

    ENDIF

    IF  NU_940T_SUPPORT

    ; Call Protection Unit initialization function

    BL      INT_Protect_Initialize

    ENDIF ; NU_940T_SUPPORT

    IF ((:LNOT: NU_MMU_MODE) :LAND: (NU_720T_SUPPORT :LOR: NU_920T_SUPPORT))

    ; Call memory management unit initialization

    BL      INT_MMU_Initialize

    ENDIF

    IF NU_CLKSPD_SUPPORT

    ; Call the function that updates bus and processor clock speeds

    BL      INT_Clkspd_Initialize
    
    ENDIF 

    ; ************ END TARGET SPECIFIC SECTION **************

    ; Restore working register from stack

    LDMIA   sp!,{lr}

    ; Return to caller

    BX      lr


;************************************************************************
;*
;*  FUNCTION
;*
;*      INT_Interrupts_Initialize
;*
;*  DESCRIPTION
;*
;*      This assembly function initializes the interrupt controller
;*      and any system set-up required to allow Nucleus PLUS to handle
;*      interrupts.  This includes copying the vector table, setting-up
;*      system registers, clearing pending interrupts, setting registers
;*      within the interrupt controller, etc.
;*
;*  CALLED BY
;*
;*      INT_Initialize
;*
;*  CALLS
;*
;*      None
;*
;*  INPUTS
;*
;*      None
;*
;*  OUTPUTS
;*
;*      None
;*
;*  REGISTERS MODIFIED
;*
;*      None
;*
;*  HISTORY
;*
;*      NAME            DATE            REMARKS
;*
;*      C. March    07/15/2003      Released Version 1.14.9
;************************************************************************
;static VOID    INT_Interrupts_Initialize(void)

INT_Interrupts_Initialize

    ; Save working registers on stack

    STMDB   sp!,{lr}

    ; ************ START TARGET SPECIFIC SECTION **************

    ; Call function to set-up global variable to access interrupt controller registers
    ; based on core module placement on stack

    BL      INT_Setup_Core_Module

    IF NU_ROM_SUPPORT

    ; Get the base for the Core module registers 

    LDR     r1, =HDR_CNTRL_BASE

    ; Each core module has interrupts for the Debug communication channels
    ; Must ensure these are disabled first

    LDR     r2, =INT_CLEAR_VALUE
    STR     r2, [r1, #HDR_IRQ_ENABLE_CLR]
    STR     r2, [r1, #HDR_FIQ_ENABLE_CLR]

    ENDIF ;NU_ROM_SUPPORT

    ; Get base address of core module interrupt registers

    LDR     r3, =INT_Module_IRQ_Base
    LDR     r3, [r3]

    ; Get the clear value and clear both the IRQ and FIQ interrupts for this module

    LDR     r2, =INT_CLEAR_VALUE
    STR     r2, [r3, #INT_CLEAR_OFFSET]     ; Clear IRQs
    ADD     r3, r3, #0x20                   ; Adjust address into FIQ area
    STR     r2, [r3, #INT_CLEAR_OFFSET]     ; Clear FIQs

    IF  (NU_ROM_SUPPORT :LOR: NU_MODULE_SUPPORT)

    ; Copy vector table to address 0x00000000

    MOV     r8, #0x00                       ; Pickup address of vector table (0x00000000)
    LDR     r9, =INT_Vectors                ; Pickup address of our vector table
    LDMIA   r9!,{r0-r7}                     ; Load vector table values into registers
    STMIA   r8!,{r0-r7}                     ; Store vector table values at correct address
    LDMIA   r9!,{r0-r7}                     ; Load vector table values into registers
    STMIA   r8!,{r0-r7}                     ; Store vector table values at correct address

    ENDIF   ; NU_ROM_SUPPORT :LOR: NU_MODULE_SUPPORT

    ; ************ END TARGET SPECIFIC SECTION **************

    ; Save working registers on stack

    LDMIA   sp!,{lr}

    ; Return to caller

    BX      lr


;************************************************************************
;*
;*  FUNCTION
;*
;*      INT_Timer_Initialize
;*
;*  DESCRIPTION
;*
;*      This assembly function is responsible for enabling a HW timer
;*      to generate the Nucleus 10ms timer interrupt (tick).  This
;*      includes setting-up the timer HW registers, P