📄 int.s
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;************************************************************************
;*
;* Copyright Mentor Graphics Corporation 2003
;* All Rights Reserved.
;*
;* THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS
;* THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS
;* SUBJECT TO LICENSE TERMS.
;*
;************************************************************************
;************************************************************************
;*
;* FILE NAME VERSION
;*
;* int.s Nucleus PLUS\Integrator\ADS 1.14.9
;*
;* COMPONENT
;*
;* IN - Initialization
;*
;* DESCRIPTION
;*
;* This file contains the target processor dependent initialization
;* routines and data.
;*
;* GLOBAL FUNCTIONS
;*
;* *****************************
;* * GENERIC FUNCTIONS *
;* *****************************
;*
;* INT_Vectors_Loaded Returns a NU_TRUE if all the
;* default vectors are loaded
;* INT_Setup_Vector Sets up an actual vector
;* INT_Retrieve_Shell Retrieves Interrupt shell
;* for specified vector
;* __user_initial_stackheap Returns start address of heap
;*
;* *****************************
;* * TARGET SPECIFIC FUNCTIONS *
;* *****************************
;*
;* None
;*
;* LOCAL FUNCTIONS
;*
;* *****************************
;* * GENERIC FUNCTIONS *
;* *****************************
;*
;* INT_Initialize Target initialization
;* INT_Undef_Inst Undefined Instruction Exception
;* handler
;* INT_Software Software Interrupt handler
;* INT_Prefetch_Abort Prefetch Abort Exeption handler
;* INT_Data_Abort Data Abort Exception handler
;* INT_Reserved Reserved Excetption handler
;* INT_IRQ_Shell Shell for all IRQ handlers
;* that use NU_Register_LISR
;* INT_FIQ_Shell Shell for all FIQ handlers
;* that use NU_Register_LISR
;* INT_Spurious_Interrupt Handler for spurious interrupts
;* (IRQ or FIQ)
;* INT_C_Memory_Initialize Initializes necessary C memory
;* to include clearing BSS section
;* INT_ROM_Data_Copy Copies initialized data from
;* ROM to RAM when running from
;* ROM
;* INT_Clear_BSS Clears initialized data (BSS)
;* INT_System_Initialize Initializes Nucleus System
;* variables
;*
;* *****************************
;* * TARGET SPECIFIC FUNCTIONS *
;* *****************************
;*
;* INT_IRQ IRQ Exception handler
;* INT_FIQ FIQ Exception handler
;* INT_Timer_Interrupt Timer interrupt target specific
;* handler
;* INT_Target_Initialize Initializes the target H/W
;* INT_HW_Memory_Initialize Initializes the target memory
;* INT_Protect_Initialize Initializes the 940T Protection
;* Unit
;* INT_Interrupts_Initialize Initializes interrupts for
;* Nucleus PLUS
;* INT_Timer_Initialize Initializes the Nucleus Timer
;* interrupt
;* INT_Clkspd_Initialize Increases CM bus and processor clock
;* speeds over CM defaults
;*
;************************************************************************
;**********************************
;* INCLUDE ASSEMBLY CONSTANTS *
;**********************************
INCLUDE asm_defs.inc
;******************************************************
;* INCLUDE files dependent on compile time switches *
;******************************************************
IF NU_MMU_MODE
INCLUDE ../../MMU/inc/mm_defs.inc ; MMU constants
INCLUDE ../../MMU/inc/mm_extr.inc
ENDIF
;**********************************
;* EXTERNAL VARIABLE DECLARATIONS *
;**********************************
;extern VOID *TCD_System_Stack
;extern VOID *TCT_System_Limit
;extern VOID *TMD_HISR_Stack_Ptr
;extern UNSIGNED TMD_HISR_Stack_Size
;extern INT TMD_HISR_Priority
;extern INT Image$$bss$$ZI$$Base
;extern INT Image$$bss$$ZI$$Limit
;extern INT Image$$text$$Limit
;extern INT Image$$data$$Base
IMPORT TCD_System_Stack
IMPORT TCT_System_Limit
IMPORT TMD_HISR_Stack_Ptr
IMPORT TMD_HISR_Stack_Size
IMPORT TMD_HISR_Priority
; Import linker produced labels
IMPORT |Image$$bss$$ZI$$Base|
IMPORT |Image$$bss$$ZI$$Limit|
IMPORT |Image$$text$$Limit|
IMPORT |Image$$data$$Base|
;**********************************
;* EXTERNAL FUNCTION DECLARATIONS *
;**********************************
;extern VOID INC_Initialize(VOID *first_available_memory)
;extern VOID TCT_Interrupt_Context_Save(VOID)
;extern VOID TCT_Interrupt_Context_Restore(VOID)
;extern VOID TCC_Dispatch_LISR(INT vector_number)
;extern VOID TMT_Timer_Interrupt(void)
IMPORT INC_Initialize
IMPORT TCT_Interrupt_Context_Save
IMPORT TCT_Interrupt_Context_Restore
IMPORT TCC_Dispatch_LISR
IMPORT TMT_Timer_Interrupt
IF NU_SUPERV_USER_MODE
IMPORT EHT_Software_Interrupt ; SWI exception handler
ENDIF
IF NU_MMU_MODE
IMPORT EHT_Prefetch_Abort
IMPORT EHT_Data_Abort
ENDIF
;**********************************
;* GLOBAL VARIABLE DECLARATIONS *
;**********************************
AREA INT_Data, DATA, NOINIT
; Define the initialization flag that indicates whether or not all of the
; default vectors have been loaded during initialization.
;INT INT_Loaded_Flag;
EXPORT INT_Loaded_Flag
INT_Loaded_Flag
DCD 0
; Define a counter used to track the number of spurious interrupts. Spurious
; interrupts occur when an interrupt is generated, but no interrupts are
; shown to be pending in the interrupt controller
;INT INT_Spurious_Count;
EXPORT INT_Spurious_Count
INT_Spurious_Count
DCD 0
AREA INT_Data_Init, DATA
; The following global variables are used to keep track
; of the base address values for IRQ / FIQ registers. These
; addresses vary depending on the position of the Core Module
; within the stack on the Integrator AP platform.
;INT INT_Module_IRQ_Base
EXPORT INT_Module_IRQ_Base
INT_Module_IRQ_Base
DCD IRQ0_BASE
;INT INT_Module_FIQ_Base
EXPORT INT_Module_FIQ_Base
INT_Module_FIQ_Base
DCD FIQ0_BASE
;**********************************
;* VECTOR TABLE *
;**********************************
AREA vectors, CODE
; Define entry point for debugger / code
ENTRY
; Define standard ARM vector table
INT_Vectors
LDR PC, INT_Reset_Addr
LDR PC, INT_Undef_Addr
LDR PC, INT_Software_Addr
LDR PC, INT_Prefetch_Addr
LDR PC, INT_Data_Addr
LDR PC, INT_Reserved_Addr
LDR PC, INT_IRQ_Addr
LDR PC, INT_FIQ_Addr
INT_Reset_Addr
DCD INT_Initialize
INT_Undef_Addr
DCD INT_Undef_Inst
IF NU_SUPERV_USER_MODE
INT_Software_Addr
DCD EHT_Software_Interrupt
ELSE
INT_Software_Addr
DCD INT_Software
ENDIF
IF NU_MMU_MODE
INT_Prefetch_Addr
DCD EHT_Prefetch_Abort
INT_Data_Addr
DCD EHT_Data_Abort
ELSE
INT_Prefetch_Addr
DCD INT_Prefetch_Abort
INT_Data_Addr
DCD INT_Data_Abort
ENDIF
INT_Reserved_Addr
DCD INT_Reserved
INT_IRQ_Addr
DCD INT_IRQ
INT_FIQ_Addr
DCD INT_FIQ
;**********************************
;* INTERRUPT TABLES *
;**********************************
AREA interrupt_tables, DATA
; The following table is used by the IRQ handler to determine
; the interrupt service routine address for each IRQ vector number.
; The default ISR allows the use of NU_Register_LISR to associate
; an interrupt handler with a paricular vector number.
; ************ START TARGET SPECIFIC SECTION **************
INT_IRQ_Vectors
DCD INT_IRQ_Shell ; Vector 0
DCD INT_IRQ_Shell ; Vector 1
DCD INT_IRQ_Shell ; Vector 2
DCD INT_IRQ_Shell ; Vector 3
DCD INT_IRQ_Shell ; Vector 4
DCD INT_IRQ_Shell ; Vector 5
DCD INT_Timer_Interrupt ; Vector 6
DCD INT_IRQ_Shell ; Vector 7
DCD INT_IRQ_Shell ; Vector 8
DCD INT_IRQ_Shell ; Vector 9
DCD INT_IRQ_Shell ; Vector 10
DCD INT_IRQ_Shell ; Vector 11
DCD INT_IRQ_Shell ; Vector 12
DCD INT_IRQ_Shell ; Vector 13
DCD INT_IRQ_Shell ; Vector 14
DCD INT_IRQ_Shell ; Vector 15
DCD INT_IRQ_Shell ; Vector 16
DCD INT_IRQ_Shell ; Vector 17
DCD INT_IRQ_Shell ; Vector 18
DCD INT_IRQ_Shell ; Vector 19
DCD INT_IRQ_Shell ; Vector 20
DCD INT_IRQ_Shell ; Vector 21
; The following table is used by the FIQ handler to determine
; the interrupt service routine address for each FIQ vector number.
; The default ISR allows the use of NU_Register_LISR to associate
; an interrupt handler with a paricular vector number.
IF NU_FIQ_SUPPORT
INT_FIQ_Vectors
DCD INT_FIQ_Shell ; Vector 0
DCD INT_FIQ_Shell ; Vector 1
DCD INT_FIQ_Shell ; Vector 2
DCD INT_FIQ_Shell ; Vector 3
DCD INT_FIQ_Shell ; Vector 4
DCD INT_FIQ_Shell ; Vector 5
DCD INT_FIQ_Shell ; Vector 6
DCD INT_FIQ_Shell ; Vector 7
DCD INT_FIQ_Shell ; Vector 8
DCD INT_FIQ_Shell ; Vector 9
DCD INT_FIQ_Shell ; Vector 10
DCD INT_FIQ_Shell ; Vector 11
DCD INT_FIQ_Shell ; Vector 12
DCD INT_FIQ_Shell ; Vector 13
DCD INT_FIQ_Shell ; Vector 14
DCD INT_FIQ_Shell ; Vector 15
DCD INT_FIQ_Shell ; Vector 16
DCD INT_FIQ_Shell ; Vector 17
DCD INT_FIQ_Shell ; Vector 18
DCD INT_FIQ_Shell ; Vector 19
DCD INT_FIQ_Shell ; Vector 20
DCD INT_FIQ_Shell ; Vector 21
ENDIF ; NU_FIQ_SUPPORT
; The following table defines the order in which pending
; interrupts will be serviced. The first entry is the highest
; priority (serviced first) and priority decreases for each
; entry as you move down the table. This table is used to allow
; interrupt nesting.
INT_Interrupt_Priority
DCD IRQ_TIMERINT1_VECTOR
DCD IRQ_PCIINT3_VECTOR
DCD IRQ_PCIINT2_VECTOR
DCD IRQ_PCIINT1_VECTOR
DCD IRQ_PCIINT0_VECTOR
DCD IRQ_UARTINT1_VECTOR
DCD IRQ_UARTINT0_VECTOR
DCD IRQ_APCINT_VECTOR
DCD IRQ_PCILBINT_VECTOR
DCD IRQ_ENUMINT_VECTOR
DCD IRQ_DEGINT_VECTOR
DCD IRQ_LINT_VECTOR
DCD IRQ_EXPINT3_VECTOR
DCD IRQ_EXPINT2_VECTOR
DCD IRQ_EXPINT1_VECTOR
DCD IRQ_EXPINT0_VECTOR
DCD IRQ_RTCINT_VECTOR
DCD IRQ_TIMERINT2_VECTOR
DCD IRQ_TIMERINT0_VECTOR
DCD IRQ_MOUSEINT_VECTOR
DCD IRQ_KBDINT_VECTOR
DCD IRQ_SOFTINT_VECTOR
INT_Interrupt_Priority_End
IF ((:LNOT: NU_MMU_MODE) :LAND: (NU_720T_SUPPORT :LOR: NU_920T_SUPPORT))
;**********************************
;* MMU TRANSLATION TABLE DECLARION*
;**********************************
AREA mmu_ttb, DATA, ALIGN = 14
; The following directive and label allocates space for the
; MMU Translation Table if PLUS is using / setting-up the
; MMU
ALIGN TTB_BASE_ALIGN
INT_MMU_TTB_Start
SPACE TTB_SIZE
; Define the areas of memory to cache when enabling the MMU with PLUS
EXPORT INT_Translation
INT_Translation
DCD 0x00000C0A
DCD 0x00100C0A
DCD 0x00200C0A
DCD 0x00300C0A
DCD 0x00400C0A
DCD 0x00500C0A
DCD 0x00600C0A
DCD 0x00700C0A
DCD 0x00800C0A
DCD 0x00900C0A
DCD 0x00A00C0A
DCD 0x00B00C0A
DCD 0x00C00C0A
DCD 0x00D00C0A
DCD 0x00E00C0A
DCD 0x00F00C0A
INT_Translation_End
; ************ END TARGET SPECIFIC SECTION **************
ENDIF ; ((:LNOT: NU_MMU_MODE) :LAND: (NU_720T_SUPPORT :LOR: NU_920T_SUPPORT))
;**********************************
;* SYSTEM STACK DECLARATION *
;**********************************
AREA system_stack, DATA, NOINIT
; The following directive and label allocate space for the
; Nucleus system stack. The system stack is used during
; initialization and during all interrupt service routines.
SPACE SYSTEM_STACK_SIZE
ALIGN 4
INT_System_SP
DCD 0
SPACE SYSTEM_STACK_SIZE
ALIGN 4
INT_System_User_SP
DCD 0
;**********************************
;* TIMER HISR STACK DECLARATION *
;**********************************
AREA hisr_stack, DATA, NOINIT
; The following label and directive allocate space for the
; Nucleus Timer HISR stack
SPACE HISR_STACK_SIZE
ALIGN 4
INT_HISR_Stack_Start
;**********************************
;* IRQ STACK DECLARATION *
;**********************************
AREA irq_stack, DATA, NOINIT
; The following directive and label allocate space for the
; IRQ stack. The IRQ stack is used to save a sub-set of
; registers during initial interrupt handling. This stack
; also holds interrupt controller mask register information
; to allow for interrupt nesting.
SPACE IRQ_STACK_SIZE
ALIGN 4
INT_Irq_SP
DCD 0
;**********************************
;* FIQ STACK DECLARATION *
;**********************************
AREA fiq_stack, DATA, NOINIT
; The following directive and label allocate space for the
; FIQ stack. The FIQ stack is used to save a sub-set of
; registers during initial interrupt handling. This stack
; also holds interrupt controller mask register information
; to allow for interrupt nesting.
SPACE FIQ_STACK_SIZE
ALIGN 4
INT_Fiq_SP
DCD 0
;**********************************
;* ABORT STACK DECLARATION *
;**********************************
AREA abort_stack, DATA, NOINIT
; The following directive and label allocate space for the
; Abort stack.
SPACE ABORT_STACK_SIZE
ALIGN 4
IF NU_MMU_MODE
EXPORT INT_Abort_SP
ENDIF
INT_Abort_SP
DCD 0
;**********************************
;* UNDEFINED STACK DECLARATION *
;**********************************
AREA undef_stack, DATA, NOINIT
; The following directive and label allocate space for the
; Undefined Instruction exception stack.
SPACE UNDEF_STACK_SIZE
ALIGN 4
INT_Undefined_SP
DCD 0
;************************************
;* HEAP DECLARATION *
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