asm_defs.inc

test file nucleus source

                                            ; Bit 6   = 1  = Periodic Timer
                                            ; Bit 5:4 = 00 = unused
                                            ; Bit 3:2 = 01 = div by 16 prescale
                                            ; Bit 1:0 = 00 = unused
TIMER_CNTRL_DISABLE     EQU     0x00        ; Value to disable timer
TIMER1_INT_MASK         EQU     0x0040      ; Mask to clear / enable timer interrupt

;************************************
;*  TARGET INTERRUPT CONSTANTS      *
;************************************

IRQ0_BASE               EQU     0x14000000
IRQ1_BASE               EQU     0x14000040
IRQ2_BASE               EQU     0x14000080
IRQ3_BASE               EQU     0x140000C0
INT_STATUS_OFFSET       EQU     0x00
INT_ENABLE_OFFSET       EQU     0x08
INT_CLEAR_OFFSET        EQU     0x0C
INT_CLEAR_VALUE         EQU     0xFFFFFFFF
FIQ0_BASE               EQU     0x14000020  
FIQ1_BASE               EQU     0x14000060
FIQ2_BASE               EQU     0x140000A0
FIQ3_BASE               EQU     0x140000E0

; Constants utilized by interrupt handler for nesting interrupts

MASK1_STACK_OFFSET      EQU     24          ; INT MASK register
INT_BASE_STACK_OFFSET   EQU     28          ; IRQ Base address register value
NUM_MASK_REGS           EQU     2           ; Number of mask register (1 mask register
                                            ; and base address of interrupt
                                            ; control register for core module)
MASK_REG_SPACE          EQU     (NUM_MASK_REGS * 4)

;**********************************
;* MMU CONSTANTS                  *
;**********************************

TTB_BASE_ALIGN          EQU     0x4000      ; TTB must be aligned on 16K boundry
TTB_SIZE                EQU     0x4000      ; TTB is 16K bytes in size
TTB_ALL_ACCESS          EQU     0x00000C12  ; All access / no Instruction/Data cache
TTB_SECTION_STEP        EQU     0x00100000  ; Step 1 MB for each memory section
DOMAIN_ACCESS           EQU     0x00000003  ; Domain 0 is a manager domain (no permission faults)

    IF NU_720T_SUPPORT

MMU_ENABLE              EQU     0x00000005  ; Enable MMU, data/instruction cache (no write buffer)

    ELSE

MMU_ENABLE              EQU     0x00001805  ; Enable MMU, data/instruction cache (no write buffer)

    ENDIF

;************************************
;*  NUCLEUS INTERRUPT CONSTANTS     *
;************************************

; Vector numbers used by Nucleus Plus (bit position in pending register)

IRQ_APCINT_VECTOR       EQU     21
IRQ_PCILBINT_VECTOR     EQU     20
IRQ_ENUMINT_VECTOR      EQU     19
IRQ_DEGINT_VECTOR       EQU     18
IRQ_LINT_VECTOR         EQU     17
IRQ_PCIINT3_VECTOR      EQU     16
IRQ_PCIINT2_VECTOR      EQU     15
IRQ_PCIINT1_VECTOR      EQU     14
IRQ_PCIINT0_VECTOR      EQU     13
IRQ_EXPINT3_VECTOR      EQU     12
IRQ_EXPINT2_VECTOR      EQU     11
IRQ_EXPINT1_VECTOR      EQU     10
IRQ_EXPINT0_VECTOR      EQU     9
IRQ_RTCINT_VECTOR       EQU     8
IRQ_TIMERINT2_VECTOR    EQU     7
IRQ_TIMERINT1_VECTOR    EQU     6
IRQ_TIMERINT0_VECTOR    EQU     5
IRQ_MOUSEINT_VECTOR     EQU     4
IRQ_KBDINT_VECTOR       EQU     3
IRQ_UARTINT1_VECTOR     EQU     2
IRQ_UARTINT0_VECTOR     EQU     1
IRQ_SOFTINT_VECTOR      EQU     0

;***********************************
;* MACROS                          *
;***********************************

    ; This macro is used to unnest interrupts.  It switches to the correct
    ; interrupt mode (FIQ/IRQ), removes the interrupt controller mask registers
    ; off the interrupt stack, restores the interrupt controller mask values,
    ; and returns back to the mode it was in before involking the macro.
    
    MACRO   
    UNNEST_INTERRUPT    $INT_MODE
    
    ; Switch to correct mode

    MRS     r0,CPSR                         ; Pickup current CPSR
    ORR     r0,r0,#LOCKOUT                  ; Lock-out interrupts
    BIC     r1,r0,#MODE_MASK                ; Clear the mode bits (preserve
                                            ; current mode in r0)
    ORR     r1,r1,#$INT_MODE                ; Set the new mode bits
    MSR     CPSR_cxsf,r1                    ; Switch to correct mode

    ; ************ START TARGET SPECIFIC SECTION **************
    
    ; Get interrupt masks from stack

    LDMIA   sp!,{r1,r2}                     ; Get mask value and base
                                            ; address of IRQ / FIQ registers
                                            
    STR     r1,[r2,#INT_ENABLE_OFFSET]      ; Re-enable all lower priority 
                                            ; interrupts

    ; ************ END TARGET SPECIFIC SECTION **************

    ; Return back to correct original mode with interrupts locked-out

    MSR     CPSR_cxsf,r0

    MEND    ; UNNEST_INTERRUPT


    ; This macro is used to unnest minimal context save interrupts.
    ; It removes the interrupt controller mask registers from the stack frame,
    ; restores the interrupt mask register values, restores the minimally
    ; saved registers (saved in INT_IRQ or INT_FIQ) and adjusts the
    ; stack pointer to its pre-interrupt state.
    
    MACRO   
    UNNEST_MIN_INTERRUPT    

    ; ************ START TARGET SPECIFIC SECTION **************
    
    MRS     r0,CPSR                         ; Pickup current CPSR
    AND     r0,r0,#MODE_MASK                ; Clear the mode bits (preserve
                                            ; current mode in r0)

    ; Get interrupt mask and interrupt base register address from stack

    LDR     r1,[sp,#MASK1_STACK_OFFSET]
    LDR     r2,[sp,#INT_BASE_STACK_OFFSET]

    ; Update mask registers

    STR     r1,[r2,#INT_ENABLE_OFFSET]      ; Re-enable all lower priority 
                                            ; interrupts

    ; ************ END TARGET SPECIFIC SECTION **************

    ; Restore registers r0-r5 from stack

    LDMIA   sp!,{r0-r5}

    ; Adjust stack to remove space saved
    ; for mask registers

    ADD     sp,sp, #MASK_REG_SPACE

    MEND    ; UNNEST_MIN_INTERRUPT

;*********************************************
;*  TC_TCB and TC_HCB STRUCT OFFSET DEFINES  *
;*********************************************

TC_CREATED              EQU     0x0         ; Node for linking to created task list
TC_ID                   EQU     0xC         ; Internal TCB ID
TC_NAME                 EQU     0x10        ; Task name
TC_STATUS               EQU     0x18        ; Task status
TC_DELAYED_SUSPEND      EQU     0x19        ; Delayed task suspension
TC_PRIORITY             EQU     0x1A        ; Task priority
TC_PREEMPTION           EQU     0x1B        ; Task preemption enable
TC_SCHEDULED            EQU     0x1C        ; Task scheduled count
TC_CUR_TIME_SLICE       EQU     0x20        ; Current time slice
TC_STACK_START          EQU     0x24        ; Stack starting address
TC_STACK_END            EQU     0x28        ; Stack ending address
TC_STACK_POINTER        EQU     0x2C        ; Task stack pointer
TC_STACK_SIZE           EQU     0x30        ; Task stack's size
TC_STACK_MINIMUM        EQU     0x34        ; Minimum stack size
TC_CURRENT_PROTECT      EQU     0x38        ; Current protection
TC_SAVED_STACK_PTR      EQU     0x3C        ; Previous stack pointer
TC_ACTIVE_NEXT          EQU     0x3C        ; Next activated HISR
TC_TIME_SLICE           EQU     0x40        ; Task time slice value
TC_ACTIVATION_COUNT     EQU     0x40        ; Activation counter
TC_HISR_ENTRY           EQU     0x44        ; HISR entry function
TC_HISR_SU_MODE         EQU     0x58        ; Sup/User mode indicator for HISRs
TC_HISR_MODULE          EQU     0x5C        ; Module identifier for HISR's
TC_SU_MODE              EQU     0xA8        ; Sup/User mode indicator for Tasks
TC_MODULE               EQU     0xAC        ; Module identifier for Tasks

TC_TCB_PTR              EQU     0x00        ; Owner of protection
TC_THREAD_WAIT          EQU     0x04        ; Waiting thread flag

;*********************************************
;*       TC_TCB and TC_HCB ID DEFINES        *
;*********************************************

TC_TASK_ID              EQU     0x5441534B  ; Redefined in assembly to determine if
TC_HISR_ID              EQU     0x48495352  ; current thread is a HISR or task.

;*********************************************
;*           Module Setup defines            *
;*********************************************
MS_TARGET               EQU     0x24        ; module support offset for
                                            ; level 1 base

    END