asm_defs.inc

test file nucleus source

;************************************************************************
;*                                                                       
;*               Copyright Mentor Graphics Corporation 2003              
;*                         All Rights Reserved.                          
;*                                                                       
;* THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS  
;* THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS   
;* SUBJECT TO LICENSE TERMS.                                             
;*                                                                       
;************************************************************************

;************************************************************************
;*                                                                       
;* FILE NAME                                  VERSION                    
;*                                                                       
;*      asm_defs.inc                  Nucleus PLUS\Integrator\ADS 1.14.9 
;*                                                                       
;* COMPONENT                                                             
;*                                                                       
;*      IN - Initialization                                              
;*                                                                       
;* DESCRIPTION                                                           
;*                                                                       
;*      This file contains the target processor dependent initialization 
;*      values used in int.s, tct.s, and tmt.s                      
;*                                                                       
;* DATA STRUCTURES                                                       
;*                                                                       
;*      NONE                                                             
;*                                                                       
;* FUNCTIONS                                                             
;*                                                                       
;*      NONE                                                             
;*                                                                       
;* DEPENDENCIES                                                          
;*                                                                       
;*      NONE                                                             
;*                                                                       
;************************************************************************

;***********************************
;* TARGET BUILD OPTIONS            *
;***********************************

    GBLL        NU_ROM_SUPPORT 
NU_ROM_SUPPORT      SETL    {FALSE}         ; Set to TRUE for support to run from ROM

    GBLL        NU_SUPERV_USER_MODE         ; When TRUE this will set mode
NU_SUPERV_USER_MODE SETL    {FALSE}         ; switching to user/system modes
                                            ; Only valid on 720T and 920T

    GBLL        NU_MODULE_SUPPORT           ; When TRUE this will allow the
NU_MODULE_SUPPORT   SETL    {FALSE}         ; generic API for MMU to run without
                                            ; using the hardware
                                            ; Only valid on 720T and 920T

    GBLL        NU_MMU_MODE                 ; When TRUE this will make the MMU
NU_MMU_MODE         SETL    {FALSE}         ; API use the hardware
                                            ; Only valid on 720T and 920T

    GBLL        NU_UNDEF_INSTR              ; Set to TRUE to set up the stack for the undefined mode
NU_UNDEF_INSTR      SETL    {FALSE}

    GBLL        NU_FIQ_SUPPORT              ; Set to TRUE to enable FIQ nested interrupt
NU_FIQ_SUPPORT      SETL    {FALSE}         ; handling / functionality

    GBLL        INCLUDE_PROVIEW
INCLUDE_PROVIEW     SETL    {FALSE}         ; Set to TRUE to enable Proview/Surroundview hooks

    GBLL        NU_CLKSPD_SUPPORT           ; Set to TRUE to increase bus and clock speed on
NU_CLKSPD_SUPPORT   SETL    {FALSE}         ; the core module you are using.  The core module
                                            ; must be designated using one of the defines below
                                            ; or setting this to TRUE will have no effect.

    GBLL        NU_7TDMI_SUPPORT            ; Define as TRUE when using the 7TDMI core module
NU_7TDMI_SUPPORT    SETL    {FALSE}         ; for increased CM bus and clock speed

    GBLL        NU_720T_SUPPORT             ; Set to TRUE to enable additional support
NU_720T_SUPPORT     SETL    {FALSE}         ; for the ARM720T processor (caching)

    GBLL        NU_920T_SUPPORT             ; Set to TRUE to enable additional support
NU_920T_SUPPORT     SETL    {FALSE}         ; for the ARM920T processor (caching)

    GBLL        NU_940T_SUPPORT             ; Set to TRUE to enable additional support
NU_940T_SUPPORT     SETL    {FALSE}         ; for the ARM940T processor (caching)

    GBLL        NU_966E_SUPPORT             ; Define as TRUE when using the 966E processor
NU_966E_SUPPORT     SETL    {FALSE}         ; and NU_ROM_SUPPORT is defined as true.

    GBLL        NU_TEST2_SUPPORT
NU_TEST2_SUPPORT      SETL    {FALSE}

    GBLL        NU_TEST3_SUPPORT
NU_TEST3_SUPPORT      SETL    {FALSE}
;*****************************
;* NUCLEUS SYSTEM CONSTANTS  *
;*****************************
HEAP_SIZE               EQU     1024        ; Heap used by certain library functions
HISR_STACK_SIZE         EQU     1024        ; Define timer HISR stack size
SYSTEM_STACK_SIZE       EQU     1024        ; Define the system stack size
SUP_STACK_SIZE          EQU     1024        ; Define the user/system stack size
IRQ_STACK_SIZE          EQU     256         ; Define the IRQ stack size
FIQ_STACK_SIZE          EQU     256         ; Define the FIQ stack size
ABORT_STACK_SIZE        EQU     256         ; Define the ABORT stack size
UNDEF_STACK_SIZE        EQU     256         ; Define the UNDEF stack size
INT_STACK_SIZE          EQU     72          ; Size of interrupt stack frame (in bytes)
SOL_STACK_SIZE          EQU     48          ; Size of solicited stack frame (in bytes)
HISR_PRIORITY           EQU     2           ; Timer HISR has priority of 2 (lowest)

;***********************************
;* TARGET INITIALIZATION CONSTANTS *
;***********************************

; CPSR bit / mask constants

LOCKOUT                 EQU     0x000000C0  ; Interrupt lockout value
LOCK_MSK                EQU     0x000000C0  ; Value to mask lockout bits
MODE_MASK               EQU     0x0000001F  ; Processor Mode Mask
SYS_MODE                EQU     0x0000001F  ; System Mode (SYS)
SUP_MODE                EQU     0x00000013  ; Supervisor Mode (SVC)
USR_MODE                EQU     0x00000010  ; User Mode(USR)
IRQ_MODE                EQU     0x00000012  ; Interrupt Mode (IRQ)
FIQ_MODE                EQU     0x00000011  ; Fast Interrupt Mode (FIQ)
UNDEF_MODE              EQU     0x0000001B  ; Undefined Instruction Mode (UNDEF)
ABT_MODE                EQU     0x00000017  ; Abort Instruction Mode (ABT)
IRQ_BIT                 EQU     0x00000080  ; IRQ bit of CPSR and SPSR
FIQ_BIT                 EQU     0x00000040  ; FIQ bit of CPSR and SPSR
THUMB_BIT               EQU     0x00000020  ; THUMB Mode bit in CPSR and SPSR

; Special registers and offsets for Integrator

HDR_CNTRL_BASE          EQU     0x10000000  ; Base of header card (Core Module registers base address)
HDR_CONTROL             EQU     0x0C        ; Offset for Core Module Control register
HDR_CM_OSC              EQU     0x10000008  ; Address of CM oscillator register
HDR_CM_LOCK             EQU     0x10000014  ; Address of CM oscillator lock register
HDR_STAT                EQU     0x10        ; Offset for Core Module Status register
HDR_SDRAM_OFFSET        EQU     0x20        ; Offset for SDRAM control register
HDR_IRQ_ENABLE_CLR      EQU     0x4C        ; Offset for IRQ enable clear (debug interrupts)
HDR_FIQ_ENABLE_CLR      EQU     0x6C        ; Offset for FIQ enable clear (debug interrupts)
HDR_SPD_OFFSET          EQU     0x100       ; Offset for SDRAM SPD memory
INTEGRATOR_REMAP        EQU     0x04        ; Bit 2 of Control register is remap
INTEGRATOR_FASTBUS      EQU     0x40        ; Bit 6 of Control register is Fastbus enable bit
CM_STAT                 EQU     0x10000010  ; Core Module Status Register

; Masks and bit defines for oscillator modifications

CM_OSC_UNLOCK_VAL       EQU     0x0000A05F  ; Unlock value for CM oscillator register
CM_OSC_MASK             EQU     0xFFF00F00  ; Masks the bus and processor clock speeds to 0
CM_7TDMI_OSC            EQU     0x0005C043  ; Increased bus and processor clock speeds for the 7TDMI
CM_720T_OSC             EQU     0x00056043  ; Increased bus and processor clock speeds for the 720T
CM_920T_OSC             EQU     0x0005A076  ; Increased bus and processor clock speeds for the 920T
CM_940T_OSC             EQU     0x00050070  ; Increased bus and processor clock speeds for the 940T
CM_966E_OSC             EQU     0x00000069  ; Increased processor clock speed for the 966E-S

; Different memory size defines used by SDRAM initializtion

SDRAM_256MB             EQU     0x0100
SDRAM_128MB             EQU     0x00C0
SDRAM_64MB              EQU     0x0040
SDRAM_32MB              EQU     0x0004
SDRAM_16MB              EQU     0x0000

; 940T Specific constants (protection unit defines)

INST_CACHE_940T         EQU     0x03        ; Area 0,1 instruction cache enabled
DATA_CACHE_940T         EQU     0x09        ; Area 0,3 data cache enabled
WB_ENABLE_940T          EQU     0x09        ; Area 0,3 write buffer enabled
DATA_PROTECT_940T       EQU     0x3FFF      ; Full access to areas 0,1,2,3,4,5 and 6 (data)
INST_PROTECT_940T       EQU     0x000F      ; Full access to area 0 and 1 (instruction)
DATA_MEM0_940T          EQU     0x0000002D  ; 8 MB data area covering 0x00000000-0x007FFFFF (covers FIRST 8 MB SDRAM)
DATA_MEM1_940T          EQU     0x0080002D  ; 8 MB data area covering 0x00800000-0x00FFFFFF (covers SECOND 8 MB SDRAM )
DATA_MEM2_940T          EQU     0x10000037  ; 256 MB data area covering 0x10000000-0x1FFFFFFF (covers CM / Board registers)
DATA_MEM3_940T          EQU     0x20000035  ; 128 MB data area covering 0x20000000-0x27FFFFFF (covers FLASH)
DATA_MEM4_940T          EQU     0x28000025  ; 512 KB data area covering 0x28000000-0x287FFFFF (covers EBI SSRAM)
DATA_MEM5_940T          EQU     0x4000003B  ; 1 GB data area covering 0x40000000-0x7FFFFFFF (covers PCI addressing)
DATA_MEM6_940T          EQU     0x8080002D  ; 8 MB data area covering 0x80800000-0x80FFFFFF (covers SECOND 8 MB SDRAM (Aliased))
INST_MEM0_940T          EQU     0x0000002D  ; 8 MB instruction area covering 0x00000000-0x007FFFFF (covers FIRST 8 MB SDRAM)
INST_MEM1_940T          EQU     0x20000035  ; 128 MB instruction area covering 0x20000000-0x27FFFFFF (covers FLASH)
CNTRL_REG_940T          EQU     0x0000107D  ; I Cache and D Cache Enable / Protection Unit Enable

;******************************
;* NUCLEUS TIMER CONSTANTS    *
;******************************

TIMER_CLOCK             EQU     24000000    ; 24 MHz clock used by timers 1 and 2
TIMER_PRESCALE          EQU     16          ; Timer Prescale of 16
TIMER_INTS_PER_SEC      EQU     100         ; 100 Timer Ticks Per Second

; Calculate timer count value based on timer clock, timer pre-scale and the number
; of timer ticks per second (100 = 10 ms timer interrupt)
; The equation for this count value is:  count = (CLOCK/PRESCALE) * .010 seconds

TIMER_COUNT             EQU     (TIMER_CLOCK/TIMER_PRESCALE) / TIMER_INTS_PER_SEC

; Define timer interrupt mode (FIQ or IRQ)

TIMER_INTERRUPT_MODE    EQU     IRQ_MODE

TIMER0_BASE             EQU     0x13000000  ; Define base for all timer0 registers
TIMER1_BASE             EQU     0x13000100  ; Define base for all timer1 registers
TIMER2_BASE             EQU     0x13000200  ; Define base for all timer1 registers
TIMER_LOAD_OFFSET       EQU     0x00        ; Offset for timer load register
TIMER_VALUE_OFFSET      EQU     0x04        ; Offset for timer value register
TIMER_CNTRL_OFFSET      EQU     0x08        ; Offset to timer control register
TIMER_CLEAR_OFFSET      EQU     0x0C        ; Offset to clear timer clear register
TIMER_CLEAR_VALUE       EQU     0x01        ; Value to clear timer interrupt
TIMER1_VAL_INIT         EQU     0x3A98      ; Value of 10ms timer
                                            ; (TIMER CLOCK / 16) * 10 ms = VALUE
                                            ; (24000000 / 16) * .010 = 0x3A98
TIMER1_CTRL_INIT        EQU     0xC4        ; Bit 7   = 1  = enable timer