cstartup_sam7.lst

关于usb的一段程序

     64                                         (AT91C_CKGR_DIV & 14);
   \   0000001A   1949               LDR         R1,??AT91F_LowLevelInit_0+0xC  ;; 0xfffffc2c
   \   0000001C   194A               LDR         R2,??AT91F_LowLevelInit_0+0x10  ;; 0x1048100e
   \   0000001E   0A60               STR         R2,[R1, #+0]
     65              // Wait for PLL stabilization
     66              while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) );
   \                     ??AT91F_LowLevelInit_2:
   \   00000020   0168               LDR         R1,[R0, #+0]
   \   00000022   4907               LSL         R1,R1,#+29
   \   00000024   FCD5               BPL         ??AT91F_LowLevelInit_2
     67              // Wait until the master clock is established for the case we already
     68              // turn on the PLL
     69              while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
   \                     ??AT91F_LowLevelInit_3:
   \   00000026   0821               MOV         R1,#+8
   \   00000028   0268               LDR         R2,[R0, #+0]
   \   0000002A   0A42               TST         R2,R1
   \   0000002C   FBD0               BEQ         ??AT91F_LowLevelInit_3
     70          
     71              ///////////////////////////////////////////////////////////////////////////
     72              // Init PMC Step 3.
     73              // Selection of Master Clock MCK equal to (Processor Clock PCK) PLL/2=48MHz
     74              // The PMC_MCKR register must not be programmed in a single write operation
     75              // (see. Product Errata Sheet)
     76              ///////////////////////////////////////////////////////////////////////////
     77              AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
   \   0000002E   164A               LDR         R2,??AT91F_LowLevelInit_0+0x14  ;; 0xfffffc30
   \   00000030   0423               MOV         R3,#+4
   \   00000032   1360               STR         R3,[R2, #+0]
     78              // Wait until the master clock is established
     79              while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
   \                     ??AT91F_LowLevelInit_4:
   \   00000034   0368               LDR         R3,[R0, #+0]
   \   00000036   0B42               TST         R3,R1
   \   00000038   FCD0               BEQ         ??AT91F_LowLevelInit_4
     80          
     81              AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
   \   0000003A   1368               LDR         R3,[R2, #+0]
   \   0000003C   0324               MOV         R4,#+3
   \   0000003E   1C43               ORR         R4,R3
   \   00000040   1460               STR         R4,[R2, #+0]
     82              // Wait until the master clock is established
     83              while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
   \                     ??AT91F_LowLevelInit_5:
   \   00000042   0268               LDR         R2,[R0, #+0]
   \   00000044   0A42               TST         R2,R1
   \   00000046   FCD0               BEQ         ??AT91F_LowLevelInit_5
     84          
     85              ///////////////////////////////////////////////////////////////////////////
     86              //  Disable Watchdog (write once register)
     87              ///////////////////////////////////////////////////////////////////////////
     88              AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
   \   00000048   1048               LDR         R0,??AT91F_LowLevelInit_0+0x18  ;; 0xfffffd44
   \   0000004A   0903               LSL         R1,R1,#+12
   \   0000004C   0160               STR         R1,[R0, #+0]
     89          
     90              ///////////////////////////////////////////////////////////////////////////
     91              //  Init AIC: assign corresponding handler for each interrupt source
     92              ///////////////////////////////////////////////////////////////////////////
     93              AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
   \   0000004E   1048               LDR         R0,??AT91F_LowLevelInit_0+0x1C  ;; 0xfffff080
   \   00000050   1049               LDR         R1,??AT91F_LowLevelInit_0+0x20  ;; AT91F_Default_FIQ_handler
   \   00000052   0160               STR         R1,[R0, #+0]
     94              for (i = 1; i < 31; i++) {
   \   00000054   0120               MOV         R0,#+1
   \   00000056   0E4A               LDR         R2,??AT91F_LowLevelInit_0+0x1C  ;; 0xfffff080
   \   00000058   0F4B               LDR         R3,??AT91F_LowLevelInit_0+0x24  ;; AT91F_Default_IRQ_handler
     95                  AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
   \                     ??AT91F_LowLevelInit_6:
   \   0000005A   8100               LSL         R1,R0,#+2
   \   0000005C   5350               STR         R3,[R2, R1]
     96              }
   \   0000005E   401C               ADD         R0,R0,#+1
   \   00000060   0106               LSL         R1,R0,#+24
   \   00000062   090E               LSR         R1,R1,#+24
   \   00000064   1F29               CMP         R1,#+31
   \   00000066   F8D3               BCC         ??AT91F_LowLevelInit_6
     97              AT91C_BASE_AIC->AIC_SPU = (unsigned int) AT91F_Spurious_handler;
   \   00000068   0C48               LDR         R0,??AT91F_LowLevelInit_0+0x28  ;; 0xfffff134
   \   0000006A   0D49               LDR         R1,??AT91F_LowLevelInit_0+0x2C  ;; AT91F_Spurious_handler
   \   0000006C   0160               STR         R1,[R0, #+0]
     98          }
   \   0000006E   10BC               POP         {R4}
   \   00000070   01BC               POP         {R0}
   \   00000072   0047               BX          R0                 ;; return
   \                     ??AT91F_LowLevelInit_0:
   \   00000074   20FCFFFF           DC32        0xfffffc20
   \   00000078   01400000           DC32        0x4001
   \   0000007C   68FCFFFF           DC32        0xfffffc68
   \   00000080   2CFCFFFF           DC32        0xfffffc2c
   \   00000084   0E104810           DC32        0x1048100e
   \   00000088   30FCFFFF           DC32        0xfffffc30
   \   0000008C   44FDFFFF           DC32        0xfffffd44
   \   00000090   80F0FFFF           DC32        0xfffff080
   \   00000094   ........           DC32        AT91F_Default_FIQ_handler
   \   00000098   ........           DC32        AT91F_Default_IRQ_handler
   \   0000009C   34F1FFFF           DC32        0xfffff134
   \   000000A0   ........           DC32        AT91F_Spurious_handler

   Maximum stack usage in bytes:

     Function           CSTACK
     --------           ------
     AT91F_LowLevelInit     8


   Segment part sizes:

     Function/Label     Bytes
     --------------     -----
     AT91F_LowLevelInit  164

 
 164 bytes in segment ICODE
 
 164 bytes of CODE memory

Errors: none
Warnings: none